Lines Matching +full:clock +full:- +full:names
3 - compatible:
7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-apq8064" for apq8064
9 - "qcom,pcie-apq8084" for apq8084
10 - "qcom,pcie-msm8996" for msm8996 or apq8096
11 - "qcom,pcie-ipq4019" for ipq4019
12 - "qcom,pcie-ipq8074" for ipq8074
13 - "qcom,pcie-qcs404" for qcs404
15 - reg:
17 Value type: <prop-encoded-array>
18 Definition: Register ranges as listed in the reg-names property
20 - reg-names:
24 - "parf" Qualcomm specific registers
25 - "dbi" DesignWare PCIe registers
26 - "elbi" External local bus interface registers
27 - "config" PCIe configuration space
29 - device_type:
32 Definition: Should be "pci". As specified in designware-pcie.txt
34 - #address-cells:
37 Definition: Should be 3. As specified in designware-pcie.txt
39 - #size-cells:
42 Definition: Should be 2. As specified in designware-pcie.txt
44 - ranges:
46 Value type: <prop-encoded-array>
47 Definition: As specified in designware-pcie.txt
49 - interrupts:
51 Value type: <prop-encoded-array>
54 - interrupt-names:
59 - #interrupt-cells:
62 Definition: Should be 1. As specified in designware-pcie.txt
64 - interrupt-map-mask:
66 Value type: <prop-encoded-array>
67 Definition: As specified in designware-pcie.txt
69 - interrupt-map:
71 Value type: <prop-encoded-array>
72 Definition: As specified in designware-pcie.txt
74 - clocks:
76 Value type: <prop-encoded-array>
77 Definition: List of phandle and clock specifier pairs as listed
78 in clock-names property
80 - clock-names:
84 - "iface" Configuration AHB clock
86 - clock-names:
90 - "core" Clocks the pcie hw block
91 - "phy" Clocks the pcie PHY block
92 - clock-names:
96 - "aux" Auxiliary (AUX) clock
97 - "bus_master" Master AXI clock
98 - "bus_slave" Slave AXI clock
100 - clock-names:
104 - "pipe" Pipe Clock driving internal logic
105 - "aux" Auxiliary (AUX) clock
106 - "cfg" Configuration clock
107 - "bus_master" Master AXI clock
108 - "bus_slave" Slave AXI clock
110 - clock-names:
114 - "iface" PCIe to SysNOC BIU clock
115 - "axi_m" AXI Master clock
116 - "axi_s" AXI Slave clock
117 - "ahb" AHB clock
118 - "aux" Auxiliary clock
120 - clock-names:
124 - "iface" AHB clock
125 - "aux" Auxiliary clock
126 - "master_bus" AXI Master clock
127 - "slave_bus" AXI Slave clock
129 - resets:
131 Value type: <prop-encoded-array>
133 in reset-names property
135 - reset-names:
139 - "axi" AXI reset
140 - "ahb" AHB reset
141 - "por" POR reset
142 - "pci" PCI reset
143 - "phy" PHY reset
145 - reset-names:
149 - "core" Core reset
151 - reset-names:
155 - "axi_m" AXI master reset
156 - "axi_s" AXI slave reset
157 - "pipe" PIPE reset
158 - "axi_m_vmid" VMID reset
159 - "axi_s_xpu" XPU reset
160 - "parf" PARF reset
161 - "phy" PHY reset
162 - "axi_m_sticky" AXI sticky reset
163 - "pipe_sticky" PIPE sticky reset
164 - "pwr" PWR reset
165 - "ahb" AHB reset
166 - "phy_ahb" PHY AHB reset
168 - reset-names:
172 - "pipe" PIPE reset
173 - "sleep" Sleep reset
174 - "sticky" Core Sticky reset
175 - "axi_m" AXI Master reset
176 - "axi_s" AXI Slave reset
177 - "ahb" AHB Reset
178 - "axi_m_sticky" AXI Master Sticky reset
180 - reset-names:
184 - "axi_m" AXI Master reset
185 - "axi_s" AXI Slave reset
186 - "axi_m_sticky" AXI Master Sticky reset
187 - "pipe_sticky" PIPE sticky reset
188 - "pwr" PWR reset
189 - "ahb" AHB reset
191 - power-domains:
193 Value type: <prop-encoded-array>
198 - vdda-supply:
203 - vdda_phy-supply:
208 - vdda_refclk-supply:
212 reference clock
213 - vddpe-3v3-supply:
218 - phys:
221 Definition: List of phandle(s) as listed in phy-names property
223 - phy-names:
228 - <name>-gpios:
230 Value type: <prop-encoded-array>
232 - "perst-gpios" PCIe endpoint reset signal line
233 - "wake-gpios" PCIe endpoint wake signal line
237 compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";
242 reg-names = "dbi", "elbi", "parf", "config";
244 linux,pci-domain = <0>;
245 bus-range = <0x00 0xff>;
246 num-lanes = <1>;
247 #address-cells = <3>;
248 #size-cells = <2>;
252 interrupt-names = "msi";
253 #interrupt-cells = <1>;
254 interrupt-map-mask = <0 0 0 0x7>;
255 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
262 clock-names = "core", "iface", "phy";
268 reset-names = "axi", "ahb", "por", "pci", "phy";
269 pinctrl-0 = <&pcie_pins_default>;
270 pinctrl-names = "default";
275 compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
280 reg-names = "parf", "dbi", "elbi", "config";
282 linux,pci-domain = <0>;
283 bus-range = <0x00 0xff>;
284 num-lanes = <1>;
285 #address-cells = <3>;
286 #size-cells = <2>;
290 interrupt-names = "msi";
291 #interrupt-cells = <1>;
292 interrupt-map-mask = <0 0 0 0x7>;
293 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
301 clock-names = "iface", "master_bus", "slave_bus", "aux";
303 reset-names = "core";
304 power-domains = <&gcc PCIE0_GDSC>;
305 vdda-supply = <&pma8084_l3>;
307 phy-names = "pciephy";
308 perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
309 pinctrl-0 = <&pcie0_pins_default>;
310 pinctrl-names = "default";