Lines Matching +full:nand +full:- +full:ecc +full:- +full:mode

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip and NAND Controller Generic Binding
10   - Miquel Raynal <miquel.raynal@bootlin.com>
11   - Richard Weinberger <richard@nod.at>
14   The NAND controller should be represented with its own DT node, and
15   all NAND chips attached to this controller should be defined as
16   children nodes of the NAND controller. This representation should be
19   The ECC strength and ECC step size properties define the user
21   they request the ECC engine to correct {strength} bit errors per
24   The interpretation of these parameters is implementation-defined, so
31     pattern: "^nand-controller(@.*)?"
33   "#address-cells":
36   "#size-cells":
42   "^nand@[a-f0-9]$":
49       nand-ecc-mode:
51           - $ref: /schemas/types.yaml#/definitions/string
52           - enum: [ none, soft, hw, hw_syndrome, hw_oob_first, on-die ]
54           Desired ECC engine, either hardware (most of the time
55           embedded in the NAND controller) or software correction
57           and should be replaced by soft and nand-ecc-algo.
59       nand-ecc-algo:
61           - $ref: /schemas/types.yaml#/definitions/string
62           - enum: [ hamming, bch, rs ]
64           Desired ECC algorithm.
66       nand-bus-width:
68           - $ref: /schemas/types.yaml#/definitions/uint32
69           - enum: [ 8, 16 ]
70           - default: 8
72           Bus width to the NAND chip
74       nand-on-flash-bbt:
80           it as the device ages. Otherwise, the out-of-band area of a
85       nand-ecc-strength:
87           - $ref: /schemas/types.yaml#/definitions/uint32
88           - minimum: 1
90           Maximum number of bits that can be corrected per ECC step.
92       nand-ecc-step-size:
94           - $ref: /schemas/types.yaml#/definitions/uint32
95           - minimum: 1
97           Number of data bytes covered by a single ECC step.
99       nand-ecc-maximize:
102           Whether or not the ECC strength should be maximized. The
103           maximum ECC strength is both controller and chip
104           dependent. The ECC engine has to select the ECC config
107           only the in-band area is used by the upper layers, and you
108           want to make your NAND as reliable as possible.
110       nand-is-boot-medium:
113           Whether or not the NAND chip is a boot medium. Drivers might
114           use this information to select ECC algorithms supported by
117       nand-rb:
118         $ref: /schemas/types.yaml#/definitions/uint32-array
123       - reg
126   - "#address-cells"
127   - "#size-cells"
130   - |
131     nand-controller {
132       #address-cells = <1>;
133       #size-cells = <0>;
137       nand@0 {
139         nand-ecc-mode = "soft";
140         nand-ecc-algo = "bch";