Lines Matching +full:nand +full:- +full:ecc +full:- +full:strength
1 MTK SoCs NAND FLASH controller (NFC) DT binding
3 This file documents the device tree bindings for MTK SoCs NAND controllers.
5 the nand controller interface driver and the ECC engine driver.
10 1) NFC NAND Controller Interface (NFI):
13 The first part of NFC is NAND Controller Interface (NFI) HW.
15 - compatible: Should be one of
16 "mediatek,mt2701-nfc",
17 "mediatek,mt2712-nfc",
18 "mediatek,mt7622-nfc".
19 - reg: Base physical address and size of NFI.
20 - interrupts: Interrupts of NFI.
21 - clocks: NFI required clocks.
22 - clock-names: NFI clocks internal name.
23 - ecc-engine: Required ECC Engine node.
24 - #address-cells: NAND chip index, should be 1.
25 - #size-cells: Should be 0.
30 compatible = "mediatek,mt2701-nfc";
35 clock-names = "nfi_clk", "pad_clk";
36 ecc-engine = <&bch>;
37 #address-cells = <1>;
38 #size-cells = <0>;
42 - children nodes: NAND chips.
45 - reg: Chip Select Signal, default 0.
48 - nand-on-flash-bbt: Store BBT on NAND Flash.
49 - nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
50 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
55 - nand-ecc-strength: Number of bits to correct per ECC step.
62 The strength should be calculated as follows:
63 E = (S - F) * 8 / B
65 E : nand-ecc-strength.
71 Q : nand-ecc-step-size.
74 According to MTK NAND controller design,
75 this number depends on max ecc step size
76 that MTK NAND controller supports.
77 If max ecc step size supported is 1024,
79 ecc step size is 512, then it should be
85 - pinctrl-names: Default NAND pin GPIO setting name.
86 - pinctrl-0: GPIO setting node.
101 input-enable;
102 drive-strength = <MTK_DRIVE_8mA>;
103 bias-pull-up;
108 drive-strength = <MTK_DRIVE_8mA>;
109 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
114 drive-strength = <MTK_DRIVE_8mA>;
115 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&nand_pins_default>;
124 nand@0 {
126 nand-on-flash-bbt;
127 nand-ecc-mode = "hw";
128 nand-ecc-strength = <24>;
129 nand-ecc-step-size = <1024>;
133 NAND chip optional subnodes:
134 - Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
137 nand@0 {
139 compatible = "fixed-partitions";
140 #address-cells = <1>;
141 #size-cells = <1>;
145 read-only;
155 2) ECC Engine:
159 - compatible: Should be one of
160 "mediatek,mt2701-ecc",
161 "mediatek,mt2712-ecc",
162 "mediatek,mt7622-ecc".
163 - reg: Base physical address and size of ECC.
164 - interrupts: Interrupts of ECC.
165 - clocks: ECC required clocks.
166 - clock-names: ECC clocks internal name.
170 bch: ecc@1100e000 {
171 compatible = "mediatek,mt2701-ecc";
175 clock-names = "nfiecc_clk";