Lines Matching +full:cs +full:- +full:gpios
4 - compatible : "fsl,upm-nand".
5 - reg : should specify localbus chip select and size used for the chip.
6 - fsl,upm-addr-offset : UPM pattern offset for the address latch.
7 - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
10 - fsl,upm-wait-flags : add chip-dependent short delays after running the
13 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
15 - gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
16 (R/B#). For multi-chip devices, "n" GPIO definitions are required
18 - chip-delay : chip dependent delay for transferring data from array to
19 read registers (tR). Required if property "gpios" is not used
22 Each flash chip described may optionally contain additional sub-nodes
29 compatible = "fsl,upm-nand";
31 fsl,upm-addr-offset = <16>;
32 fsl,upm-cmd-offset = <8>;
33 gpios = <&qe_pio_e 18 0>;
36 #address-cells = <1>;
37 #size-cells = <1>;
47 #address-cells = <0>;
48 #size-cells = <0>;
49 compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand";
51 fsl,upm-addr-offset = <0x10>;
52 fsl,upm-cmd-offset = <0x08>;
53 /* Multi-chip NAND device */
54 fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
55 fsl,upm-wait-flags = <0x5>;
56 chip-delay = <25>; // in micro-seconds
59 #address-cells = <1>;
60 #size-cells = <1>;