Lines Matching +full:nand +full:- +full:ecc +full:- +full:maximize
1 * Denali NAND controller
4 - compatible : should be one of the following:
5 "altr,socfpga-denali-nand" - for Altera SOCFPGA
6 "socionext,uniphier-denali-nand-v5a" - for Socionext UniPhier (v5a)
7 "socionext,uniphier-denali-nand-v5b" - for Socionext UniPhier (v5b)
8 - reg : should contain registers location and length for data and reg.
9 - reg-names: Should contain the reg names "nand_data" and "denali_reg"
10 - #address-cells: should be 1. The cell encodes the chip select connection.
11 - #size-cells : should be 0.
12 - interrupts : The interrupt number.
13 - clocks: should contain phandle of the controller core clock, the bus
14 interface clock, and the ECC circuit clock.
15 - clock-names: should contain "nand", "nand_x", "ecc"
17 Sub-nodes:
18 Sub-nodes represent available NAND chips.
21 - reg: should contain the bank ID of the controller to which each chip
25 - nand-ecc-step-size: see nand-controller.yaml for details.
27 512 for "altr,socfpga-denali-nand"
28 1024 for "socionext,uniphier-denali-nand-v5a"
29 1024 for "socionext,uniphier-denali-nand-v5b"
30 - nand-ecc-strength: see nand-controller.yaml for details. Valid values are:
31 8, 15 for "altr,socfpga-denali-nand"
32 8, 16, 24 for "socionext,uniphier-denali-nand-v5a"
33 8, 16 for "socionext,uniphier-denali-nand-v5b"
34 - nand-ecc-maximize: see nand-controller.yaml for details
36 The chip nodes may optionally contain sub-nodes describing partitions of the
41 nand: nand@ff900000 {
42 #address-cells = <1>;
43 #size-cells = <0>;
44 compatible = "altr,socfpga-denali-nand";
46 reg-names = "nand_data", "denali_reg";
48 clock-names = "nand", "nand_x", "ecc";
51 nand@0 {