Lines Matching refs:interrupt

1 Broadcom BCM7120-style Level 2 interrupt controller
3 This interrupt controller hardware is a second level interrupt controller that
4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
7 Such an interrupt controller has the following hardware design:
9 - outputs multiple interrupts signals towards its interrupt controller parent
12   directly output an interrupt signal towards the interrupt controller parent,
13   or if they will output an interrupt signal at this 2nd level interrupt
20 - not all bits within the interrupt controller actually map to an interrupt
24 2nd level interrupt line		Outputs for the parent controller (e.g: ARM GIC)
26 0 -----[ MUX ] ------------|==========> GIC interrupt 75
29 1 -----[ MUX ] --------)---|==========> GIC interrupt 76
32 2 -----[ MUX ] --------)---|==========> GIC interrupt 77
38 7 ---------------------|---|===========> GIC interrupt 66
44                            |===========> GIC interrupt 64
56 - interrupt-controller: identifies the node as an interrupt controller
57 - #interrupt-cells: specifies the number of cells needed to encode an interrupt
59 - interrupts: specifies the interrupt line(s) in the interrupt-parent controller
60   node, valid values depend on the type of parent interrupt controller
62   are wired to this 2nd level interrupt controller, and how they match their
63   respective interrupt parents. Should match exactly the number of interrupts
73   respective interrupt outputs bypass this 2nd level interrupt controller
74   completely; it is completely transparent for the interrupt controller
79 irq0_intc: interrupt-controller@f0406800 {
81 	interrupt-parent = <&intc>;
82 	#interrupt-cells = <1>;
84 	interrupt-controller;