Lines Matching +full:interrupt +full:- +full:affinity
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller, version 3
10 - Marc Zyngier <marc.zyngier@arm.com>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
27 - const: arm,gic-v3
28 - const: arm,gic-v3
30 interrupt-controller: true
32 "#address-cells":
34 "#size-cells":
39 "#interrupt-cells":
41 Specifies the number of cells needed to encode an interrupt source.
43 If the system requires describing PPI affinity, then the value must
46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
50 The 2nd cell contains the interrupt number for the interrupt type.
51 SPI interrupts are in the range [0-987]. PPI interrupts are in the
52 range [0-15]. Extented SPI interrupts are in the range [0-1023].
53 Extended PPI interrupts are in the range [0-127].
61 interrupt is affine to. The interrupt must be a PPI, and the node
62 pointed must be a subnode of the "ppi-partitions" subnode. For
63 interrupt types other than PPI or PPIs that are not partitionned,
64 this cell must be zero. See the "ppi-partitions" node description
75 - GIC Distributor interface (GICD)
76 - GIC Redistributors (GICR), one range per redistributor region
77 - GIC CPU interface (GICC)
78 - GIC Hypervisor interface (GICH)
79 - GIC Virtual CPU interface (GICV)
87 Interrupt source of the VGIC maintenance interrupt.
90 redistributor-stride:
95 - $ref: /schemas/types.yaml#/definitions/uint64
96 - multipleOf: 0x10000
99 "#redistributor-regions":
104 - $ref: /schemas/types.yaml#/definitions/uint32
105 - maximum: 4096 # Should be enough?
107 msi-controller:
109 Only present if the Message Based Interrupt functionnality is
110 being exposed by the HW, and the mbi-ranges property present.
112 mbi-ranges:
118 - $ref: /schemas/types.yaml#/definitions/uint32-matrix
119 - items:
123 mbi-alias:
129 - $ref: /schemas/types.yaml#/definitions/uint32-array
130 - items:
134 ppi-partitions:
137 PPI affinity can be expressed as a single "ppi-partitions" node,
138 containing a set of sub-nodes.
140 "^interrupt-partition-[0-9]+$":
142 affinity:
143 $ref: /schemas/types.yaml#/definitions/phandle-array
149 - affinity
152 mbi-ranges: [ msi-controller ]
153 msi-controller: [ mbi-ranges ]
156 - compatible
157 - interrupts
158 - reg
161 "^gic-its@": false
162 "^interrupt-controller@[0-9a-f]+$": false
163 # msi-controller is preferred, but allow other names
164 "^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$":
167 GICv3 has one or more Interrupt Translation Services (ITS) that are
171 const: arm,gic-v3-its
173 msi-controller: true
175 "#msi-cells":
177 The single msi-cell is the DeviceID of the device which will generate
186 socionext,synquacer-pre-its:
189 address and size of the pre-ITS window.
191 - $ref: /schemas/types.yaml#/definitions/uint32-array
192 - items:
197 - compatible
198 - msi-controller
199 - "#msi-cells"
200 - reg
207 - |
208 gic: interrupt-controller@2cf00000 {
209 compatible = "arm,gic-v3";
210 #interrupt-cells = <3>;
211 #address-cells = <1>;
212 #size-cells = <1>;
214 interrupt-controller;
222 msi-controller;
223 mbi-ranges = <256 128>;
225 msi-controller@2c200000 {
226 compatible = "arm,gic-v3-its";
227 msi-controller;
228 #msi-cells = <1>;
233 interrupt-controller@2c010000 {
234 compatible = "arm,gic-v3";
235 #interrupt-cells = <4>;
236 #address-cells = <1>;
237 #size-cells = <1>;
239 interrupt-controller;
240 redistributor-stride = <0x0 0x40000>; // 256kB stride
241 #redistributor-regions = <2>;
243 <0x2d000000 0x800000>, // GICR 1: CPUs 0-31
244 <0x2e000000 0x800000>, // GICR 2: CPUs 32-63
250 msi-controller@2c200000 {
251 compatible = "arm,gic-v3-its";
252 msi-controller;
253 #msi-cells = <1>;
257 msi-controller@2c400000 {
258 compatible = "arm,gic-v3-its";
259 msi-controller;
260 #msi-cells = <1>;
264 ppi-partitions {
265 part0: interrupt-partition-0 {
266 affinity = <&cpu0 &cpu2>;
269 part1: interrupt-partition-1 {
270 affinity = <&cpu1 &cpu3>;