Lines Matching +full:ddc +full:- +full:i2c +full:- +full:bus
4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
20 - reset-names: Must include the following entries:
21 - host1x
23 The host1x top-level node defines a number of children, each representing one
26 - mpe: video encoder
29 - compatible: "nvidia,tegra<chip>-mpe"
30 - reg: Physical base address and length of the controller's registers.
31 - interrupts: The interrupt outputs from the controller.
32 - clocks: Must contain one entry, for the module clock.
33 See ../clocks/clock-bindings.txt for details.
34 - resets: Must contain an entry for each entry in reset-names.
36 - reset-names: Must include the following entries:
37 - mpe
39 - vi: video input
42 - compatible: "nvidia,tegra<chip>-vi"
43 - reg: Physical base address and length of the controller's registers.
44 - interrupts: The interrupt outputs from the controller.
45 - clocks: Must contain one entry, for the module clock.
46 See ../clocks/clock-bindings.txt for details.
47 - resets: Must contain an entry for each entry in reset-names.
49 - reset-names: Must include the following entries:
50 - vi
52 - epp: encoder pre-processor
55 - compatible: "nvidia,tegra<chip>-epp"
56 - reg: Physical base address and length of the controller's registers.
57 - interrupts: The interrupt outputs from the controller.
58 - clocks: Must contain one entry, for the module clock.
59 See ../clocks/clock-bindings.txt for details.
60 - resets: Must contain an entry for each entry in reset-names.
62 - reset-names: Must include the following entries:
63 - epp
65 - isp: image signal processor
68 - compatible: "nvidia,tegra<chip>-isp"
69 - reg: Physical base address and length of the controller's registers.
70 - interrupts: The interrupt outputs from the controller.
71 - clocks: Must contain one entry, for the module clock.
72 See ../clocks/clock-bindings.txt for details.
73 - resets: Must contain an entry for each entry in reset-names.
75 - reset-names: Must include the following entries:
76 - isp
78 - gr2d: 2D graphics engine
81 - compatible: "nvidia,tegra<chip>-gr2d"
82 - reg: Physical base address and length of the controller's registers.
83 - interrupts: The interrupt outputs from the controller.
84 - clocks: Must contain one entry, for the module clock.
85 See ../clocks/clock-bindings.txt for details.
86 - resets: Must contain an entry for each entry in reset-names.
88 - reset-names: Must include the following entries:
89 - 2d
91 - gr3d: 3D graphics engine
94 - compatible: "nvidia,tegra<chip>-gr3d"
95 - reg: Physical base address and length of the controller's registers.
96 - clocks: Must contain an entry for each entry in clock-names.
97 See ../clocks/clock-bindings.txt for details.
98 - clock-names: Must include the following entries:
100 - 3d
102 - 3d2 (Only required on SoCs with two 3D clocks)
103 - resets: Must contain an entry for each entry in reset-names.
105 - reset-names: Must include the following entries:
106 - 3d
107 - 3d2 (Only required on SoCs with two 3D clocks)
109 - dc: display controller
112 - compatible: "nvidia,tegra<chip>-dc"
113 - reg: Physical base address and length of the controller's registers.
114 - interrupts: The interrupt outputs from the controller.
115 - clocks: Must contain an entry for each entry in clock-names.
116 See ../clocks/clock-bindings.txt for details.
117 - clock-names: Must include the following entries:
118 - dc
120 - parent
121 - resets: Must contain an entry for each entry in reset-names.
123 - reset-names: Must include the following entries:
124 - dc
125 - nvidia,head: The number of the display controller head. This is used to
132 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
133 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
134 - nvidia,edid: supplies a binary EDID blob
135 - nvidia,panel: phandle of a display panel
137 - hdmi: High Definition Multimedia Interface
140 - compatible: "nvidia,tegra<chip>-hdmi"
141 - reg: Physical base address and length of the controller's registers.
142 - interrupts: The interrupt outputs from the controller.
143 - hdmi-supply: supply for the +5V HDMI connector pin
144 - vdd-supply: regulator for supply voltage
145 - pll-supply: regulator for PLL
146 - clocks: Must contain an entry for each entry in clock-names.
147 See ../clocks/clock-bindings.txt for details.
148 - clock-names: Must include the following entries:
149 - hdmi
151 - parent
152 - resets: Must contain an entry for each entry in reset-names.
154 - reset-names: Must include the following entries:
155 - hdmi
158 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
159 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
160 - nvidia,edid: supplies a binary EDID blob
161 - nvidia,panel: phandle of a display panel
163 - tvo: TV encoder output
166 - compatible: "nvidia,tegra<chip>-tvo"
167 - reg: Physical base address and length of the controller's registers.
168 - interrupts: The interrupt outputs from the controller.
169 - clocks: Must contain one entry, for the module clock.
170 See ../clocks/clock-bindings.txt for details.
172 - dsi: display serial interface
175 - compatible: "nvidia,tegra<chip>-dsi"
176 - reg: Physical base address and length of the controller's registers.
177 - clocks: Must contain an entry for each entry in clock-names.
178 See ../clocks/clock-bindings.txt for details.
179 - clock-names: Must include the following entries:
180 - dsi
182 - lp
183 - parent
184 - resets: Must contain an entry for each entry in reset-names.
186 - reset-names: Must include the following entries:
187 - dsi
188 - avdd-dsi-supply: phandle of a supply that powers the DSI controller
189 - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
191 ../display/tegra/nvidia,tegra114-mipi.txt.
194 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
195 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
196 - nvidia,edid: supplies a binary EDID blob
197 - nvidia,panel: phandle of a display panel
198 - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
201 - sor: serial output resource
204 - compatible: Should be:
205 - "nvidia,tegra124-sor": for Tegra124 and Tegra132
206 - "nvidia,tegra132-sor": for Tegra132
207 - "nvidia,tegra210-sor": for Tegra210
208 - "nvidia,tegra210-sor1": for Tegra210
209 - "nvidia,tegra186-sor": for Tegra186
210 - "nvidia,tegra186-sor1": for Tegra186
211 - reg: Physical base address and length of the controller's registers.
212 - interrupts: The interrupt outputs from the controller.
213 - clocks: Must contain an entry for each entry in clock-names.
214 See ../clocks/clock-bindings.txt for details.
215 - clock-names: Must include the following entries:
216 - sor: clock input for the SOR hardware
217 - out: SOR output clock
218 - parent: input for the pixel clock
219 - dp: reference clock for the SOR clock
220 - safe: safe reference for the SOR clock during power up
223 - pad: SOR pad output clock (on Tegra186 and later)
226 - source: source clock for the SOR clock (obsolete, use "out" instead)
228 - resets: Must contain an entry for each entry in reset-names.
230 - reset-names: Must include the following entries:
231 - sor
234 - nvidia,interface: index of the SOR interface
237 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
238 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
239 - nvidia,edid: supplies a binary EDID blob
240 - nvidia,panel: phandle of a display panel
241 - nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane
246 - nvidia,dpaux: phandle to a DispayPort AUX interface
248 - dpaux: DisplayPort AUX interface
249 - compatible : Should contain one of the following:
250 - "nvidia,tegra124-dpaux": for Tegra124 and Tegra132
251 - "nvidia,tegra210-dpaux": for Tegra210
252 - reg: Physical base address and length of the controller's registers.
253 - interrupts: The interrupt outputs from the controller.
254 - clocks: Must contain an entry for each entry in clock-names.
255 See ../clocks/clock-bindings.txt for details.
256 - clock-names: Must include the following entries:
257 - dpaux: clock input for the DPAUX hardware
258 - parent: reference clock
259 - resets: Must contain an entry for each entry in reset-names.
261 - reset-names: Must include the following entries:
262 - dpaux
263 - vdd-supply: phandle of a supply that powers the DisplayPort link
264 - i2c-bus: Subnode where I2C slave devices are listed. This subnode
265 must be always present. If there are no I2C slave devices, an empty
266 node should be added. See ../../i2c/i2c.txt for more information.
268 See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information
271 - vic: Video Image Compositor
272 - compatible : "nvidia,tegra<chip>-vic"
273 - reg: Physical base address and length of the controller's registers.
274 - interrupts: The interrupt outputs from the controller.
275 - clocks: Must contain an entry for each entry in clock-names.
276 See ../clocks/clock-bindings.txt for details.
277 - clock-names: Must include the following entries:
278 - vic: clock input for the VIC hardware
279 - resets: Must contain an entry for each entry in reset-names.
281 - reset-names: Must include the following entries:
282 - vic
290 compatible = "nvidia,tegra20-host1x", "simple-bus";
296 reset-names = "host1x";
298 #address-cells = <1>;
299 #size-cells = <1>;
304 compatible = "nvidia,tegra20-mpe";
309 reset-names = "mpe";
313 compatible = "nvidia,tegra20-vi";
318 reset-names = "vi";
322 compatible = "nvidia,tegra20-epp";
327 reset-names = "epp";
331 compatible = "nvidia,tegra20-isp";
336 reset-names = "isp";
340 compatible = "nvidia,tegra20-gr2d";
345 reset-names = "2d";
349 compatible = "nvidia,tegra20-gr3d";
353 reset-names = "3d";
357 compatible = "nvidia,tegra20-dc";
362 clock-names = "dc", "parent";
364 reset-names = "dc";
372 compatible = "nvidia,tegra20-dc";
377 clock-names = "dc", "parent";
379 reset-names = "dc";
387 compatible = "nvidia,tegra20-hdmi";
392 clock-names = "hdmi", "parent";
394 reset-names = "hdmi";
399 compatible = "nvidia,tegra20-tvo";
407 compatible = "nvidia,tegra20-dsi";
411 clock-names = "dsi", "parent";
413 reset-names = "dsi";