Lines Matching +full:panel +full:- +full:lvds

1 Rockchip RK3288 LVDS interface
5 - compatible: matching the soc type, one of
6 	- "rockchip,rk3288-lvds";
8 - reg: physical base address of the controller and length
10 - clocks: must include clock specifiers corresponding to entries in the
11 	clock-names property.
12 - clock-names: must contain "pclk_lvds"
14 - avdd1v0-supply: regulator phandle for 1.0V analog power
15 - avdd1v8-supply: regulator phandle for 1.8V analog power
16 - avdd3v3-supply: regulator phandle for 3.3V analog power
18 - rockchip,grf: phandle to the general register files syscon
19 - rockchip,output: "rgb", "lvds" or "duallvds", This describes the output interface
22 - pinctrl-names: must contain a "lcdc" entry.
23 - pinctrl-0: pin control group to be used for this controller.
27 The lvds has two video ports as described by
28 	Documentation/devicetree/bindings/media/video-interfaces.txt
32 - video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
33 - video port 1 for either a panel or subsequent encoder
37 lvds_panel: lvds-panel {
39 	enable-gpios = <&gpio7 21 GPIO_ACTIVE_HIGH>;
40 	data-mapping = "jeida-24";
44 			remote-endpoint = <&lvds_out_panel>;
51 	lvds: lvds@ff96c000 {
52 		compatible = "rockchip,rk3288-lvds";
56 		clock-names = "pclk_lvds";
57 		pinctrl-names = "lcdc";
58 		pinctrl-0 = <&lcdc_ctl>;
59 		avdd1v0-supply = <&vdd10_lcd>;
60 		avdd1v8-supply = <&vcc18_lcd>;
61 		avdd3v3-supply = <&vcca_33>;
64 			#address-cells = <1>;
65 			#size-cells = <0>;
72 					remote-endpoint = <&vopb_out_lvds>;
76 					remote-endpoint = <&vopl_out_lvds>;
84 					remote-endpoint = <&panel_in_lvds>;