Lines Matching refs:side
73 the ODT on the DRAM side and controller side are
77 the DRAM side driver strength in ohms. Default
81 the DRAM side ODT strength in ohms. Default value
85 the phy side CA line (incluing command line,
90 the PHY side DQ line (including DQS/DQ/DM line)
94 the PHY side ODT strength. Default value is
100 the ODT on the DRAM side and controller side are
104 the DRAM side driver strength in ohms. Default
108 the DRAM side ODT strength in ohms. Default value
112 the PHY side CA line (including command line,
117 the PHY side DQ line (including DQS/DQ/DM line)
122 the phy side odt strength, default value is
128 ddr3_odt_dis_freq, the ODT on the DRAM side and
129 controller side are both disabled.
132 the DRAM side driver strength in ohms. Default
136 the DRAM side ODT on DQS/DQ line strength in ohms.
140 the DRAM side ODT on CA line strength in ohms.
144 the PHY side CA line (including command address
149 the PHY side clock line and CS line driver
153 the PHY side DQ line (including DQS/DQ/DM line)
157 the PHY side ODT strength. Default value is