Lines Matching full:must
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
52 using blocks of up to 2 megabytes in size, it must not be placed within
53 any 2M region which must be mapped with any specific attributes.
103 little-endian and must be respected. Where image_size is zero,
134 The Image must be placed text_offset bytes from a 2MB aligned base
138 At least image_size bytes from the start of the image must be free for
144 If an initrd/initramfs is passed to the kernel at boot, it must reside
153 Before jumping into the kernel, the following conditions must be met:
168 All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
170 The CPU must be in either EL2 (RECOMMENDED in order to have access to
175 The MMU must be off.
177 The address range corresponding to the loaded kernel image must be
182 operations must be configured and may be enabled.
184 operations (not recommended) must be configured and disabled.
188 CNTFRQ must be programmed with the timer frequency and CNTVOFF must
190 kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where
195 All CPUs to be booted by the kernel must be part of the same coherency
203 the kernel image will be entered must be initialised by software at a
206 - SCR_EL3.FIQ must have the same value across all CPUs the kernel is
208 - The value of SCR_EL3.FIQ must be the same as the one present at boot
214 - ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
215 - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
219 - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
220 - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
222 - The DT or ACPI tables must describe a GICv3 interrupt controller.
229 ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0.
233 ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0.
235 - The DT or ACPI tables must describe a GICv2 interrupt controller.
240 - SCR_EL3.APK (bit 16) must be initialised to 0b1
241 - SCR_EL3.API (bit 17) must be initialised to 0b1
245 - HCR_EL2.APK (bit 40) must be initialised to 0b1
246 - HCR_EL2.API (bit 41) must be initialised to 0b1
249 timers, coherency and system registers apply to all CPUs. All CPUs must
255 - The primary CPU must jump directly to the first instruction of the
256 kernel image. The device tree blob passed by this CPU must contain
263 - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
269 device tree) polling their cpu-release-addr location, which must be
273 cpu-release-addr returns a non-zero value, the CPU must jump to this
275 value, so CPUs must convert the read value to their native endianness