Lines Matching full:one
38 entity which appears to be fetching instructions that belong to one sequence
42 First, if the whole processor can only follow one sequence of instructions (one
47 least one program at a time. The cores need not be entirely independent of each
50 one program, those programs run mostly independently of each other at the same
56 except for one have been put into idle states at the "core level" and the
61 Finally, each core in a multi-core processor may be able to follow more than one
67 (or hyper-threads specifically on Intel hardware), that each can follow one
70 by one of them, the hardware thread (or CPU) that asked for it is stopped, but
94 assigns it to one of the available CPUs to run and if there are no more runnable
96 code (from the instruction following the last one executed so far, possibly by
97 another CPU). [If there are multiple runnable tasks assigned to one CPU
104 code may cause the processor to be put into one of its idle states, if they are
127 the platform or the processor architecture and organized in a one-dimensional
137 substantial), in order to save more energy than it would save by entering one of
159 and that is the primary reason for having more than one governor in the
175 platform the kernel is running on, but there are platforms with more than one
177 majority of Intel platforms, ``intel_idle`` and ``acpi_idle``, one with
181 decision on which one of them to use has to be made early (on Intel platforms
195 multiple runnable tasks assigned to one CPU at the same time, the only way to
216 "idle" one. In other words, from the CPU scheduler perspective, the only user
245 stopped already (in one of the previous iterations of the loop), it is better
281 One of them is used when tasks previously running on the given CPU are waiting
282 for some I/O operations to complete and the other one is used when that is not
285 array is approximately 10 times wider than the previous one.
325 Now, the governor is ready to walk the list of idle states and choose one of
348 for tickless systems. It follows the same basic strategy as the ``menu`` `one
391 deeper than the given one).
394 and finds the last (deepest) one with the target residency less than or equal
396 state are compared with each other and it is preselected if the ``hits`` one is
398 duration after CPU wakeup). If the ``misses`` one is greater, the governor
414 one and finds the deepest of them with the target residency within that average.
434 supported by the processor have to be represented as a one-dimensional array of
437 is a hierarchy of units in the processor, one |struct cpuidle_state| object can
446 (say "X") at the "core" level by one core will trigger the module to try to
479 :c:type:`struct cpuidle_state_usage <cpuidle_state_usage>` one containing usage
487 objects defined for the given CPU minus one. Each of these directories
488 corresponds to one idle state object and the larger the number in its name, the
535 The :file:`disable` attribute is the only writeable one. If it contains 1, the
539 However, disabling an idle state for one CPU does not prevent it from being
543 selecting any idle states deeper than the disabled one too.]
563 this idle state and entered a shallower one instead of it (or even it did not
632 In turn, for each CPU there is only one resume latency PM QoS request
674 governor will be used instead of the default one. It is possible to force