Lines Matching +full:cpu +full:- +full:centric

9 as CPU cache coherence, but may have different performance. For example,
14 characteristics.  Some memory may share the same node as a CPU, and others
20  +------------------+     +------------------+
21  | Compute Node 0   +-----+ Compute Node 1   |
23  +--------+---------+     +--------+---------+
25  +--------+---------+     +--------+---------+
27  +------------------+     +--------+---------+
35 performance when accessing a given memory target. Each initiator-target
47 	# symlinks -v /sys/devices/system/node/nodeX/access0/targets/
48 	relative: /sys/devices/system/node/nodeX/access0/targets/nodeY -> ../../nodeY
50 	# symlinks -v /sys/devices/system/node/nodeY/access0/initiators/
51 	relative: /sys/devices/system/node/nodeY/access0/initiators/nodeX -> ../../nodeX
77 	# tree -P "read*|write*" /sys/devices/system/node/nodeY/access0/initiators/
79 	|-- read_bandwidth
80 	|-- read_latency
81 	|-- write_bandwidth
82 	`-- write_latency
108 This numbering is different than CPU caches where the cache level (ex:
109 L1, L2, L3) uses the CPU-side view where each increased level is lower
110 performing. In contrast, the memory cache level is centric to the last
112 nearer to the CPU, and further from far memory.
114 The memory-side caches are not directly addressable by software. When
133 a memory-side cache, or that information is not accessible to the kernel.
148 	|-- index1
149 	|   |-- indexing
150 	|   |-- line_size
151 	|   |-- size
152 	|   `-- write_policy
154 The "indexing" will be 0 if it is a direct-mapped cache, and non-zero
155 for any other indexed based, multi-way associativity.
162 The "write_policy" will be 0 for write-back, and non-zero for
163 write-through caching.
170 - Section 5.2.27