Lines Matching full:that
5 This document describes the semantics of the DMA attributes that are
21 useful, suppose that a device does a DMA write to indicate that data is
29 DMA_ATTR_WEAK_ORDERING specifies that reads and writes to the mapping
30 may be weakly ordered, that is that reads and writes may pass each other.
33 those that do not will simply ignore the attribute and exhibit default
39 DMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be
43 those that do not will simply ignore the attribute and exhibit default
51 you are guaranteeing to the platform that you have all the correct and
63 that you won't dereference the pointer returned by dma_alloc_attr(). You
64 can treat it as a cookie that must be passed to dma_mmap_attrs() and
65 dma_free_attrs(). Make sure that both of these also get this attribute
69 DMA_ATTR_NO_KERNEL_MAPPING, those that do not will simply ignore the
83 (usually it means that the cache has been flushed or invalidated
90 the CPU cache for the given buffer assuming that it has been already
108 This is a hint to the DMA-mapping subsystem that it's probably not worth
109 the time to try to allocate memory to in a way that gives better TLB
113 - You know that the accesses to this memory won't thrash the TLB.
114 You might know that the accesses are likely to be sequential or
115 that they aren't sequential but it's unlikely you'll ping-pong
116 between many addresses that are likely to be in different physical
118 - You know that the penalty of TLB misses while accessing the
122 - You know that the DMA mapping is fairly transitory. If you expect
127 Setting this hint doesn't guarantee that you won't get huge pages, but it
128 means that we won't try quite as hard to get them.
142 and can actually flood the system logs with error messages that aren't any
156 subsystem that the buffer is fully accessible at the elevated privilege