Lines Matching +full:0 +full:x0000000080000000
13 asm volatile("mfspr %0," _str(rn) \
15 #define mtspr(rn, v) asm volatile("mtspr " _str(rn) ",%0" : \
25 #define MMCR0_PMAO 0x00000080
26 #define MMCR0_PMAE 0x04000000
27 #define MMCR0_FC 0x80000000
33 #define SPRN_BESCRR 802 /* Branch event status & control REset (1 bits set to 0) */
36 #define BESCR_PMEO 0x1 /* PMU Event-based exception Occurred */
37 #define BESCR_PME (0x1ul << 32) /* PMU Event-based exception Enable */
50 #define SPRN_TEXASR 0x82 /* Transaction Exception and Status Register */
51 #define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */
52 #define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */
53 #define SPRN_TAR 0x32f /* Target Address Register */
55 #define SPRN_DSCR_PRIV 0x11 /* Privilege State DSCR */
56 #define SPRN_DSCR 0x03 /* Data Stream Control Register */
61 "mtspr " __stringify(SPRN_AMR) ",%0;" \
67 #define TEXASR_FC 0xFE00000000000000
68 #define TEXASR_FP 0x0100000000000000
69 #define TEXASR_DA 0x0080000000000000
70 #define TEXASR_NO 0x0040000000000000
71 #define TEXASR_FO 0x0020000000000000
72 #define TEXASR_SIC 0x0010000000000000
73 #define TEXASR_NTC 0x0008000000000000
74 #define TEXASR_TC 0x0004000000000000
75 #define TEXASR_TIC 0x0002000000000000
76 #define TEXASR_IC 0x0001000000000000
77 #define TEXASR_IFC 0x0000800000000000
78 #define TEXASR_ABT 0x0000000100000000
79 #define TEXASR_SPD 0x0000000080000000
80 #define TEXASR_HV 0x0000000020000000
81 #define TEXASR_PR 0x0000000010000000
82 #define TEXASR_FS 0x0000000008000000
83 #define TEXASR_TE 0x0000000004000000
84 #define TEXASR_ROT 0x0000000002000000
97 #define VSX_XX1(xs, ra, rb) (((xs) & 0x1f) << 21 | ((ra) << 16) | \
99 #define STXVD2X(xs, ra, rb) .long (0x7c000798 | VSX_XX1((xs), (ra), (rb)))
100 #define LXVD2X(xs, ra, rb) .long (0x7c000698 | VSX_XX1((xs), (ra), (rb)))
123 "lfs 0, 0(%[" #_asm_symbol_name_addr "]);" \
124 "lfs 1, 0(%[" #_asm_symbol_name_addr "]);" \
125 "lfs 2, 0(%[" #_asm_symbol_name_addr "]);" \
126 "lfs 3, 0(%[" #_asm_symbol_name_addr "]);" \
127 "lfs 4, 0(%[" #_asm_symbol_name_addr "]);" \
128 "lfs 5, 0(%[" #_asm_symbol_name_addr "]);" \
129 "lfs 6, 0(%[" #_asm_symbol_name_addr "]);" \
130 "lfs 7, 0(%[" #_asm_symbol_name_addr "]);" \
131 "lfs 8, 0(%[" #_asm_symbol_name_addr "]);" \
132 "lfs 9, 0(%[" #_asm_symbol_name_addr "]);" \
133 "lfs 10, 0(%[" #_asm_symbol_name_addr "]);" \
134 "lfs 11, 0(%[" #_asm_symbol_name_addr "]);" \
135 "lfs 12, 0(%[" #_asm_symbol_name_addr "]);" \
136 "lfs 13, 0(%[" #_asm_symbol_name_addr "]);" \
137 "lfs 14, 0(%[" #_asm_symbol_name_addr "]);" \
138 "lfs 15, 0(%[" #_asm_symbol_name_addr "]);" \
139 "lfs 16, 0(%[" #_asm_symbol_name_addr "]);" \
140 "lfs 17, 0(%[" #_asm_symbol_name_addr "]);" \
141 "lfs 18, 0(%[" #_asm_symbol_name_addr "]);" \
142 "lfs 19, 0(%[" #_asm_symbol_name_addr "]);" \
143 "lfs 20, 0(%[" #_asm_symbol_name_addr "]);" \
144 "lfs 21, 0(%[" #_asm_symbol_name_addr "]);" \
145 "lfs 22, 0(%[" #_asm_symbol_name_addr "]);" \
146 "lfs 23, 0(%[" #_asm_symbol_name_addr "]);" \
147 "lfs 24, 0(%[" #_asm_symbol_name_addr "]);" \
148 "lfs 25, 0(%[" #_asm_symbol_name_addr "]);" \
149 "lfs 26, 0(%[" #_asm_symbol_name_addr "]);" \
150 "lfs 27, 0(%[" #_asm_symbol_name_addr "]);" \
151 "lfs 28, 0(%[" #_asm_symbol_name_addr "]);" \
152 "lfs 29, 0(%[" #_asm_symbol_name_addr "]);" \
153 "lfs 30, 0(%[" #_asm_symbol_name_addr "]);" \
154 "lfs 31, 0(%[" #_asm_symbol_name_addr "]);"