5  * Copyright (C) 2020, Red Hat, Inc.
59 #define for_each_sublist(c, s)							\  argument
60 	for ((s) = &(c)->sublists[0]; (s)->regs; ++(s))
77 static const char *config_name(struct vcpu_config *c)  in config_name()  argument
82 	if (c->name)  in config_name()
83 		return c->name;  in config_name()
85 	for_each_sublist(c, s)  in config_name()
88 	c->name = malloc(len);  in config_name()
91 	for_each_sublist(c, s) {  in config_name()
94 		strcat(c->name + len, s->name);  in config_name()
96 		c->name[len - 1] = '+';  in config_name()
98 	c->name[len - 1] = '\0';  in config_name()
100 	return c->name;  in config_name()
103 static bool has_cap(struct vcpu_config *c, long capability)  in has_cap()  argument
107 	for_each_sublist(c, s)  in has_cap()
143 	strcat(p + n, strstr(template, "##") + 2);  in str_with_index()
150 #define CORE_REGS_XX_NR_WORDS	2
151 #define CORE_SPSR_XX_NR_WORDS	2
154 static const char *core_id_to_str(struct vcpu_config *c, __u64 id)  in core_id_to_str()  argument
165 		TEST_ASSERT(idx < 31, "%s: Unexpected regs.regs index: %lld", config_name(c), idx);  in core_id_to_str()
180 		TEST_ASSERT(idx < KVM_NR_SPSR, "%s: Unexpected spsr index: %lld", config_name(c), idx);  in core_id_to_str()
185 		TEST_ASSERT(idx < 32, "%s: Unexpected fp_regs.vregs index: %lld", config_name(c), idx);  in core_id_to_str()
193 	TEST_FAIL("%s: Unknown core reg id: 0x%llx", config_name(c), id);  in core_id_to_str()
197 static const char *sve_id_to_str(struct vcpu_config *c, __u64 id)  in sve_id_to_str()  argument
207 	TEST_ASSERT(i == 0, "%s: Currently we don't expect slice > 0, reg id 0x%llx", config_name(c), id);  in sve_id_to_str()
214 			    "%s: Unexpected bits set in SVE ZREG id: 0x%llx", config_name(c), id);  in sve_id_to_str()
220 			    "%s: Unexpected bits set in SVE PREG id: 0x%llx", config_name(c), id);  in sve_id_to_str()
224 			    "%s: Unexpected bits set in SVE FFR id: 0x%llx", config_name(c), id);  in sve_id_to_str()
231 static void print_reg(struct vcpu_config *c, __u64 id)  in print_reg()  argument
237 		    "%s: KVM_REG_ARM64 missing in reg id: 0x%llx", config_name(c), id);  in print_reg()
269 			  config_name(c), (id & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT, id);  in print_reg()
274 		printf("\tKVM_REG_ARM64 | %s | KVM_REG_ARM_CORE | %s,\n", reg_size, core_id_to_str(c, id));  in print_reg()
278 			    "%s: Unexpected bits set in DEMUX reg id: 0x%llx", config_name(c), id);  in print_reg()
289 			    "%s: Unexpected bits set in SYSREG reg id: 0x%llx", config_name(c), id);  in print_reg()
294 			    "%s: Unexpected bits set in FW reg id: 0x%llx", config_name(c), id);  in print_reg()
298 		if (has_cap(c, KVM_CAP_ARM_SVE))  in print_reg()
299 			printf("\t%s,\n", sve_id_to_str(c, id));  in print_reg()
301 …TEST_FAIL("%s: KVM_REG_ARM64_SVE is an unexpected coproc type in reg id: 0x%llx", config_name(c), …  in print_reg()
305 			  config_name(c), (id & KVM_REG_ARM_COPROC_MASK) >> KVM_REG_ARM_COPROC_SHIFT, id);  in print_reg()
366 static void prepare_vcpu_init(struct vcpu_config *c, struct kvm_vcpu_init *init)  in prepare_vcpu_init()  argument
370 	for_each_sublist(c, s)  in prepare_vcpu_init()
375 static void finalize_vcpu(struct kvm_vm *vm, uint32_t vcpuid, struct vcpu_config *c)  in finalize_vcpu()  argument
380 	for_each_sublist(c, s) {  in finalize_vcpu()
388 static void check_supported(struct vcpu_config *c)  in check_supported()  argument
392 	for_each_sublist(c, s) {  in check_supported()
394 			fprintf(stderr, "%s: %s not available, skipping tests\n", config_name(c), s->name);  in check_supported()
404 static void run_test(struct vcpu_config *c)  in run_test()  argument
412 	check_supported(c);  in run_test()
415 	prepare_vcpu_init(c, &init);  in run_test()
417 	finalize_vcpu(vm, 0, c);  in run_test()
430 				print_reg(c, id);  in run_test()
457 			printf("%s: Failed to get ", config_name(c));  in run_test()
458 			print_reg(c, reg.id);  in run_test()
464 		for_each_sublist(c, s) {  in run_test()
469 					printf("%s: Failed to reject (ret=%d, errno=%d) ", config_name(c), ret, errno);  in run_test()
470 					print_reg(c, reg.id);  in run_test()
481 				printf("%s: Failed to set ", config_name(c));  in run_test()
482 				print_reg(c, reg.id);  in run_test()
489 	for_each_sublist(c, s)  in run_test()
494 	for_each_sublist(c, s) {  in run_test()
506 		printf("%s: Number blessed registers: %5lld\n", config_name(c), blessed_n);  in run_test()
507 		printf("%s: Number registers:         %5lld\n", config_name(c), reg_list->n);  in run_test()
513 		       "list with the following lines:\n\n", config_name(c), new_regs);  in run_test()
515 			print_reg(c, reg_list->reg[i]);  in run_test()
521 		       "The following lines are missing registers:\n\n", config_name(c), missing_regs);  in run_test()
523 			print_reg(c, blessed_reg[i]);  in run_test()
530 		    config_name(c), missing_regs, failed_get, failed_set, failed_reject);  in run_test()
532 	pr_info("%s: PASS\n", config_name(c));  in run_test()
541 	struct vcpu_config *c;  in help()  local
551 		c = vcpu_configs[i];  in help()
553 	"                               '%s'\n", config_name(c));  in help()
567 	struct vcpu_config *c;  in parse_config()  local
574 		c = vcpu_configs[i];  in parse_config()
575 		if (strcmp(config_name(c), &config[9]) == 0)  in parse_config()
582 	return c;  in parse_config()
587 	struct vcpu_config *c, *sel = NULL;  in main()  local
615 		c = vcpu_configs[i];  in main()
616 		if (sel && c != sel)  in main()
622 			run_test(c);  in main()
645 	KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[2]),
681 	KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(spsr[2]),
688 	KVM_REG_ARM_FW_REG(2),
690 	ARM64_SYS_REG(3, 3, 14, 3, 2),	/* CNTV_CVAL_EL0 */
691 	ARM64_SYS_REG(3, 3, 14, 0, 2),
697 	ARM64_SYS_REG(2, 0, 0, 0, 4),
698 	ARM64_SYS_REG(2, 0, 0, 0, 5),
699 	ARM64_SYS_REG(2, 0, 0, 0, 6),
700 	ARM64_SYS_REG(2, 0, 0, 0, 7),
701 	ARM64_SYS_REG(2, 0, 0, 1, 4),
702 	ARM64_SYS_REG(2, 0, 0, 1, 5),
703 	ARM64_SYS_REG(2, 0, 0, 1, 6),
704 	ARM64_SYS_REG(2, 0, 0, 1, 7),
705 	ARM64_SYS_REG(2, 0, 0, 2, 0),	/* MDCCINT_EL1 */
706 	ARM64_SYS_REG(2, 0, 0, 2, 2),	/* MDSCR_EL1 */
707 	ARM64_SYS_REG(2, 0, 0, 2, 4),
708 	ARM64_SYS_REG(2, 0, 0, 2, 5),
709 	ARM64_SYS_REG(2, 0, 0, 2, 6),
710 	ARM64_SYS_REG(2, 0, 0, 2, 7),
711 	ARM64_SYS_REG(2, 0, 0, 3, 4),
712 	ARM64_SYS_REG(2, 0, 0, 3, 5),
713 	ARM64_SYS_REG(2, 0, 0, 3, 6),
714 	ARM64_SYS_REG(2, 0, 0, 3, 7),
715 	ARM64_SYS_REG(2, 0, 0, 4, 4),
716 	ARM64_SYS_REG(2, 0, 0, 4, 5),
717 	ARM64_SYS_REG(2, 0, 0, 4, 6),
718 	ARM64_SYS_REG(2, 0, 0, 4, 7),
719 	ARM64_SYS_REG(2, 0, 0, 5, 4),
720 	ARM64_SYS_REG(2, 0, 0, 5, 5),
721 	ARM64_SYS_REG(2, 0, 0, 5, 6),
722 	ARM64_SYS_REG(2, 0, 0, 5, 7),
723 	ARM64_SYS_REG(2, 0, 0, 6, 4),
724 	ARM64_SYS_REG(2, 0, 0, 6, 5),
725 	ARM64_SYS_REG(2, 0, 0, 6, 6),
726 	ARM64_SYS_REG(2, 0, 0, 6, 7),
727 	ARM64_SYS_REG(2, 0, 0, 7, 4),
728 	ARM64_SYS_REG(2, 0, 0, 7, 5),
729 	ARM64_SYS_REG(2, 0, 0, 7, 6),
730 	ARM64_SYS_REG(2, 0, 0, 7, 7),
731 	ARM64_SYS_REG(2, 0, 0, 8, 4),
732 	ARM64_SYS_REG(2, 0, 0, 8, 5),
733 	ARM64_SYS_REG(2, 0, 0, 8, 6),
734 	ARM64_SYS_REG(2, 0, 0, 8, 7),
735 	ARM64_SYS_REG(2, 0, 0, 9, 4),
736 	ARM64_SYS_REG(2, 0, 0, 9, 5),
737 	ARM64_SYS_REG(2, 0, 0, 9, 6),
738 	ARM64_SYS_REG(2, 0, 0, 9, 7),
739 	ARM64_SYS_REG(2, 0, 0, 10, 4),
740 	ARM64_SYS_REG(2, 0, 0, 10, 5),
741 	ARM64_SYS_REG(2, 0, 0, 10, 6),
742 	ARM64_SYS_REG(2, 0, 0, 10, 7),
743 	ARM64_SYS_REG(2, 0, 0, 11, 4),
744 	ARM64_SYS_REG(2, 0, 0, 11, 5),
745 	ARM64_SYS_REG(2, 0, 0, 11, 6),
746 	ARM64_SYS_REG(2, 0, 0, 11, 7),
747 	ARM64_SYS_REG(2, 0, 0, 12, 4),
748 	ARM64_SYS_REG(2, 0, 0, 12, 5),
749 	ARM64_SYS_REG(2, 0, 0, 12, 6),
750 	ARM64_SYS_REG(2, 0, 0, 12, 7),
751 	ARM64_SYS_REG(2, 0, 0, 13, 4),
752 	ARM64_SYS_REG(2, 0, 0, 13, 5),
753 	ARM64_SYS_REG(2, 0, 0, 13, 6),
754 	ARM64_SYS_REG(2, 0, 0, 13, 7),
755 	ARM64_SYS_REG(2, 0, 0, 14, 4),
756 	ARM64_SYS_REG(2, 0, 0, 14, 5),
757 	ARM64_SYS_REG(2, 0, 0, 14, 6),
758 	ARM64_SYS_REG(2, 0, 0, 14, 7),
759 	ARM64_SYS_REG(2, 0, 0, 15, 4),
760 	ARM64_SYS_REG(2, 0, 0, 15, 5),
761 	ARM64_SYS_REG(2, 0, 0, 15, 6),
762 	ARM64_SYS_REG(2, 0, 0, 15, 7),
763 	ARM64_SYS_REG(2, 4, 0, 7, 0),	/* DBGVCR32_EL2 */
767 	ARM64_SYS_REG(3, 0, 0, 1, 2),	/* ID_DFR0_EL1 */
773 	ARM64_SYS_REG(3, 0, 0, 2, 0),	/* ID_ISAR0_EL1 */
774 	ARM64_SYS_REG(3, 0, 0, 2, 1),	/* ID_ISAR1_EL1 */
775 	ARM64_SYS_REG(3, 0, 0, 2, 2),	/* ID_ISAR2_EL1 */
776 	ARM64_SYS_REG(3, 0, 0, 2, 3),	/* ID_ISAR3_EL1 */
777 	ARM64_SYS_REG(3, 0, 0, 2, 4),	/* ID_ISAR4_EL1 */
778 	ARM64_SYS_REG(3, 0, 0, 2, 5),	/* ID_ISAR5_EL1 */
779 	ARM64_SYS_REG(3, 0, 0, 2, 6),	/* ID_MMFR4_EL1 */
780 	ARM64_SYS_REG(3, 0, 0, 2, 7),	/* ID_ISAR6_EL1 */
783 	ARM64_SYS_REG(3, 0, 0, 3, 2),	/* MVFR2_EL1 */
791 	ARM64_SYS_REG(3, 0, 0, 4, 2),
799 	ARM64_SYS_REG(3, 0, 0, 5, 2),
807 	ARM64_SYS_REG(3, 0, 0, 6, 2),
815 	ARM64_SYS_REG(3, 0, 0, 7, 2),	/* ID_AA64MMFR2_EL1 */
823 	ARM64_SYS_REG(3, 0, 1, 0, 2),	/* CPACR_EL1 */
824 	ARM64_SYS_REG(3, 0, 2, 0, 0),	/* TTBR0_EL1 */
825 	ARM64_SYS_REG(3, 0, 2, 0, 1),	/* TTBR1_EL1 */
826 	ARM64_SYS_REG(3, 0, 2, 0, 2),	/* TCR_EL1 */
829 	ARM64_SYS_REG(3, 0, 5, 2, 0),	/* ESR_EL1 */
832 	ARM64_SYS_REG(3, 0, 10, 2, 0),	/* MAIR_EL1 */
839 	ARM64_SYS_REG(3, 2, 0, 0, 0),	/* CSSELR_EL1 */
840 	ARM64_SYS_REG(3, 3, 13, 0, 2),	/* TPIDR_EL0 */
849 	ARM64_SYS_REG(3, 0, 9, 14, 2),	/* PMINTENCLR_EL1 */
852 	ARM64_SYS_REG(3, 3, 9, 12, 2),	/* PMCNTENCLR_EL0 */
861 	ARM64_SYS_REG(3, 3, 14, 8, 2),
869 	ARM64_SYS_REG(3, 3, 14, 9, 2),
877 	ARM64_SYS_REG(3, 3, 14, 10, 2),
885 	ARM64_SYS_REG(3, 3, 14, 11, 2),
892 	ARM64_SYS_REG(3, 3, 14, 12, 2),
900 	ARM64_SYS_REG(3, 3, 14, 13, 2),
908 	ARM64_SYS_REG(3, 3, 14, 14, 2),
916 	ARM64_SYS_REG(3, 3, 14, 15, 2),
927 	KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[2]),
963 	KVM_REG_ARM64_SVE_ZREG(2, 0),
995 	KVM_REG_ARM64_SVE_PREG(2, 0),
1010 	ARM64_SYS_REG(3, 0, 1, 2, 0),   /* ZCR_EL1 */