1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
11 #include <linux/clk-provider.h>
135 #define	I2S_CGFR_I2SDIV_MAX	((1 << (I2S_CGFR_I2SDIV_BIT_H -\
136 				I2S_CGFR_I2SDIV_SHIFT)) - 1)
197 #define STM32_I2S_IS_MASTER(x)		((x)->ms_flg == I2S_MS_MASTER)
198 #define STM32_I2S_IS_SLAVE(x)		((x)->ms_flg == I2S_MS_SLAVE)
204  * struct stm32_i2s_data - private data of I2S
281 		dev_dbg(&i2s->pdev->dev, "Divider: 2*%d(div)+%d(odd) = %d\n",  in stm32_i2s_calc_clk_div()
287 		dev_err(&i2s->pdev->dev, "Wrong divider setting\n");  in stm32_i2s_calc_clk_div()
288 		return -EINVAL;  in stm32_i2s_calc_clk_div()
292 		dev_dbg(&i2s->pdev->dev,  in stm32_i2s_calc_clk_div()
296 	i2s->div = div;  in stm32_i2s_calc_clk_div()
297 	i2s->odd = odd;  in stm32_i2s_calc_clk_div()
298 	i2s->divider = divider;  in stm32_i2s_calc_clk_div()
307 	cgfr = I2S_CGFR_I2SDIV_SET(i2s->div) | (i2s->odd << I2S_CGFR_ODD_SHIFT);  in stm32_i2s_set_clk_div()
310 	return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,  in stm32_i2s_set_clk_div()
317 	struct platform_device *pdev = i2s->pdev;  in stm32_i2s_set_parent_clock()
322 		parent_clk = i2s->x11kclk;  in stm32_i2s_set_parent_clock()
324 		parent_clk = i2s->x8kclk;  in stm32_i2s_set_parent_clock()
326 	ret = clk_set_parent(i2s->i2sclk, parent_clk);  in stm32_i2s_set_parent_clock()
328 		dev_err(&pdev->dev,  in stm32_i2s_set_parent_clock()
338 	struct stm32_i2s_data *i2s = mclk->i2s_data;  in stm32_i2smclk_round_rate()
345 	mclk->freq = *prate / i2s->divider;  in stm32_i2smclk_round_rate()
347 	return mclk->freq;  in stm32_i2smclk_round_rate()
355 	return mclk->freq;  in stm32_i2smclk_recalc_rate()
362 	struct stm32_i2s_data *i2s = mclk->i2s_data;  in stm32_i2smclk_set_rate()
373 	mclk->freq = rate;  in stm32_i2smclk_set_rate()
381 	struct stm32_i2s_data *i2s = mclk->i2s_data;  in stm32_i2smclk_enable()
383 	dev_dbg(&i2s->pdev->dev, "Enable master clock\n");  in stm32_i2smclk_enable()
385 	return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,  in stm32_i2smclk_enable()
392 	struct stm32_i2s_data *i2s = mclk->i2s_data;  in stm32_i2smclk_disable()
394 	dev_dbg(&i2s->pdev->dev, "Disable master clock\n");  in stm32_i2smclk_disable()
396 	regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, I2S_CGFR_MCKOE, 0);  in stm32_i2smclk_disable()
411 	struct device *dev = &i2s->pdev->dev;  in stm32_i2s_add_mclk_provider()
412 	const char *pname = __clk_get_name(i2s->i2sclk);  in stm32_i2s_add_mclk_provider()
418 		return -ENOMEM;  in stm32_i2s_add_mclk_provider()
423 		return -ENOMEM;  in stm32_i2s_add_mclk_provider()
430 	while (*s && *s != '_' && (i < (STM32_I2S_NAME_LEN - 7))) {  in stm32_i2s_add_mclk_provider()
436 	mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0);  in stm32_i2s_add_mclk_provider()
437 	mclk->i2s_data = i2s;  in stm32_i2s_add_mclk_provider()
438 	hw = &mclk->hw;  in stm32_i2s_add_mclk_provider()
441 	ret = devm_clk_hw_register(&i2s->pdev->dev, hw);  in stm32_i2s_add_mclk_provider()
446 	i2s->i2smclk = hw->clk;  in stm32_i2s_add_mclk_provider()
455 	struct platform_device *pdev = i2s->pdev;  in stm32_i2s_isr()
460 	regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr);  in stm32_i2s_isr()
461 	regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier);  in stm32_i2s_isr()
465 		dev_dbg(&pdev->dev, "Spurious IRQ sr=0x%08x, ier=0x%08x\n",  in stm32_i2s_isr()
470 	regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,  in stm32_i2s_isr()
474 		dev_dbg(&pdev->dev, "Overrun\n");  in stm32_i2s_isr()
479 		dev_dbg(&pdev->dev, "Underrun\n");  in stm32_i2s_isr()
484 		dev_dbg(&pdev->dev, "Frame error\n");  in stm32_i2s_isr()
486 	spin_lock(&i2s->irq_lock);  in stm32_i2s_isr()
487 	if (err && i2s->substream)  in stm32_i2s_isr()
488 		snd_pcm_stop_xrun(i2s->substream);  in stm32_i2s_isr()
489 	spin_unlock(&i2s->irq_lock);  in stm32_i2s_isr()
548 	dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);  in stm32_i2s_set_dai_fmt()
569 		dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",  in stm32_i2s_set_dai_fmt()
571 		return -EINVAL;  in stm32_i2s_set_dai_fmt()
589 		dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",  in stm32_i2s_set_dai_fmt()
591 		return -EINVAL;  in stm32_i2s_set_dai_fmt()
597 		i2s->ms_flg = I2S_MS_SLAVE;  in stm32_i2s_set_dai_fmt()
600 		i2s->ms_flg = I2S_MS_MASTER;  in stm32_i2s_set_dai_fmt()
603 		dev_err(cpu_dai->dev, "Unsupported mode %#x\n",  in stm32_i2s_set_dai_fmt()
605 		return -EINVAL;  in stm32_i2s_set_dai_fmt()
608 	i2s->fmt = fmt;  in stm32_i2s_set_dai_fmt()
609 	return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,  in stm32_i2s_set_dai_fmt()
619 	dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz. mode: %s, dir: %s\n",  in stm32_i2s_set_sysclk()
625 		if (!i2s->i2smclk) {  in stm32_i2s_set_sysclk()
626 			dev_dbg(cpu_dai->dev, "No MCLK registered\n");  in stm32_i2s_set_sysclk()
633 			if (i2s->mclk_rate) {  in stm32_i2s_set_sysclk()
634 				clk_rate_exclusive_put(i2s->i2smclk);  in stm32_i2s_set_sysclk()
635 				i2s->mclk_rate = 0;  in stm32_i2s_set_sysclk()
637 			return regmap_update_bits(i2s->regmap,  in stm32_i2s_set_sysclk()
645 		ret = clk_set_rate_exclusive(i2s->i2smclk, freq);  in stm32_i2s_set_sysclk()
647 			dev_err(cpu_dai->dev, "Could not set mclk rate\n");  in stm32_i2s_set_sysclk()
650 		ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,  in stm32_i2s_set_sysclk()
653 			i2s->mclk_rate = freq;  in stm32_i2s_set_sysclk()
670 		clk_set_parent(i2s->i2sclk, i2s->x11kclk);  in stm32_i2s_configure_clock()
672 		clk_set_parent(i2s->i2sclk, i2s->x8kclk);  in stm32_i2s_configure_clock()
673 	i2s_clock_rate = clk_get_rate(i2s->i2sclk);  in stm32_i2s_configure_clock()
687 	if (i2s->mclk_rate) {  in stm32_i2s_configure_clock()
689 					     i2s->mclk_rate);  in stm32_i2s_configure_clock()
694 		if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==  in stm32_i2s_configure_clock()
699 		ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr);  in stm32_i2s_configure_clock()
715 	return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG,  in stm32_i2s_configure_clock()
740 		dev_err(cpu_dai->dev, "Unexpected format %d", format);  in stm32_i2s_configure()
741 		return -EINVAL;  in stm32_i2s_configure()
755 	ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,  in stm32_i2s_configure()
761 	cfg1 = I2S_CFG1_FTHVL_SET(fthlv - 1);  in stm32_i2s_configure()
763 	return regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,  in stm32_i2s_configure()
774 	spin_lock_irqsave(&i2s->irq_lock, flags);  in stm32_i2s_startup()
775 	i2s->substream = substream;  in stm32_i2s_startup()
776 	spin_unlock_irqrestore(&i2s->irq_lock, flags);  in stm32_i2s_startup()
778 	if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A)  in stm32_i2s_startup()
779 		snd_pcm_hw_constraint_single(substream->runtime,  in stm32_i2s_startup()
782 	ret = clk_prepare_enable(i2s->i2sclk);  in stm32_i2s_startup()
784 		dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);  in stm32_i2s_startup()
788 	return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,  in stm32_i2s_startup()
801 		dev_err(cpu_dai->dev, "Configuration returned error %d\n", ret);  in stm32_i2s_hw_params()
815 	bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);  in stm32_i2s_trigger()
824 		dev_dbg(cpu_dai->dev, "start I2S %s\n",  in stm32_i2s_trigger()
828 		regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,  in stm32_i2s_trigger()
831 		ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,  in stm32_i2s_trigger()
834 			dev_err(cpu_dai->dev, "Error %d enabling I2S\n", ret);  in stm32_i2s_trigger()
838 		ret = regmap_write_bits(i2s->regmap, STM32_I2S_CR1_REG,  in stm32_i2s_trigger()
841 			dev_err(cpu_dai->dev, "Error %d starting I2S\n", ret);  in stm32_i2s_trigger()
845 		regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,  in stm32_i2s_trigger()
848 		spin_lock(&i2s->lock_fd);  in stm32_i2s_trigger()
849 		i2s->refcount++;  in stm32_i2s_trigger()
855 			if (STM32_I2S_IS_MASTER(i2s) && i2s->refcount == 1)  in stm32_i2s_trigger()
857 				regmap_write(i2s->regmap,  in stm32_i2s_trigger()
860 		spin_unlock(&i2s->lock_fd);  in stm32_i2s_trigger()
865 		regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier);  in stm32_i2s_trigger()
870 		dev_dbg(cpu_dai->dev, "stop I2S %s\n",  in stm32_i2s_trigger()
874 			regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,  in stm32_i2s_trigger()
878 			regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,  in stm32_i2s_trigger()
882 		spin_lock(&i2s->lock_fd);  in stm32_i2s_trigger()
883 		i2s->refcount--;  in stm32_i2s_trigger()
884 		if (i2s->refcount) {  in stm32_i2s_trigger()
885 			spin_unlock(&i2s->lock_fd);  in stm32_i2s_trigger()
889 		ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,  in stm32_i2s_trigger()
892 			dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret);  in stm32_i2s_trigger()
893 			spin_unlock(&i2s->lock_fd);  in stm32_i2s_trigger()
896 		spin_unlock(&i2s->lock_fd);  in stm32_i2s_trigger()
899 		regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,  in stm32_i2s_trigger()
903 		return -EINVAL;  in stm32_i2s_trigger()
915 	clk_disable_unprepare(i2s->i2sclk);  in stm32_i2s_shutdown()
917 	spin_lock_irqsave(&i2s->irq_lock, flags);  in stm32_i2s_shutdown()
918 	i2s->substream = NULL;  in stm32_i2s_shutdown()
919 	spin_unlock_irqrestore(&i2s->irq_lock, flags);  in stm32_i2s_shutdown()
924 	struct stm32_i2s_data *i2s = dev_get_drvdata(cpu_dai->dev);  in stm32_i2s_dai_probe()
925 	struct snd_dmaengine_dai_dma_data *dma_data_tx = &i2s->dma_data_tx;  in stm32_i2s_dai_probe()
926 	struct snd_dmaengine_dai_dma_data *dma_data_rx = &i2s->dma_data_rx;  in stm32_i2s_dai_probe()
929 	dma_data_tx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;  in stm32_i2s_dai_probe()
930 	dma_data_tx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_TXDR_REG;  in stm32_i2s_dai_probe()
931 	dma_data_tx->maxburst = 1;  in stm32_i2s_dai_probe()
932 	dma_data_rx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;  in stm32_i2s_dai_probe()
933 	dma_data_rx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_RXDR_REG;  in stm32_i2s_dai_probe()
934 	dma_data_rx->maxburst = 1;  in stm32_i2s_dai_probe()
979 	.name = "stm32-i2s",
985 	stream->stream_name = stream_name;  in stm32_i2s_dai_init()
986 	stream->channels_min = 1;  in stm32_i2s_dai_init()
987 	stream->channels_max = 2;  in stm32_i2s_dai_init()
988 	stream->rates = SNDRV_PCM_RATE_8000_192000;  in stm32_i2s_dai_init()
989 	stream->formats = SNDRV_PCM_FMTBIT_S16_LE |  in stm32_i2s_dai_init()
998 	dai_ptr = devm_kzalloc(&pdev->dev, sizeof(struct snd_soc_dai_driver),  in stm32_i2s_dais_init()
1001 		return -ENOMEM;  in stm32_i2s_dais_init()
1003 	dai_ptr->probe = stm32_i2s_dai_probe;  in stm32_i2s_dais_init()
1004 	dai_ptr->ops = &stm32_i2s_pcm_dai_ops;  in stm32_i2s_dais_init()
1005 	dai_ptr->id = 1;  in stm32_i2s_dais_init()
1006 	stm32_i2s_dai_init(&dai_ptr->playback, "playback");  in stm32_i2s_dais_init()
1007 	stm32_i2s_dai_init(&dai_ptr->capture, "capture");  in stm32_i2s_dais_init()
1008 	i2s->dai_drv = dai_ptr;  in stm32_i2s_dais_init()
1015 		.compatible = "st,stm32h7-i2s",
1024 	struct device_node *np = pdev->dev.of_node;  in stm32_i2s_parse_dt()
1031 		return -ENODEV;  in stm32_i2s_parse_dt()
1033 	of_id = of_match_device(stm32_i2s_ids, &pdev->dev);  in stm32_i2s_parse_dt()
1035 		i2s->regmap_conf = (const struct regmap_config *)of_id->data;  in stm32_i2s_parse_dt()
1037 		return -EINVAL;  in stm32_i2s_parse_dt()
1039 	i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in stm32_i2s_parse_dt()
1040 	if (IS_ERR(i2s->base))  in stm32_i2s_parse_dt()
1041 		return PTR_ERR(i2s->base);  in stm32_i2s_parse_dt()
1043 	i2s->phys_addr = res->start;  in stm32_i2s_parse_dt()
1046 	i2s->pclk = devm_clk_get(&pdev->dev, "pclk");  in stm32_i2s_parse_dt()
1047 	if (IS_ERR(i2s->pclk)) {  in stm32_i2s_parse_dt()
1048 		if (PTR_ERR(i2s->pclk) != -EPROBE_DEFER)  in stm32_i2s_parse_dt()
1049 			dev_err(&pdev->dev, "Could not get pclk: %ld\n",  in stm32_i2s_parse_dt()
1050 				PTR_ERR(i2s->pclk));  in stm32_i2s_parse_dt()
1051 		return PTR_ERR(i2s->pclk);  in stm32_i2s_parse_dt()
1054 	i2s->i2sclk = devm_clk_get(&pdev->dev, "i2sclk");  in stm32_i2s_parse_dt()
1055 	if (IS_ERR(i2s->i2sclk)) {  in stm32_i2s_parse_dt()
1056 		if (PTR_ERR(i2s->i2sclk) != -EPROBE_DEFER)  in stm32_i2s_parse_dt()
1057 			dev_err(&pdev->dev, "Could not get i2sclk: %ld\n",  in stm32_i2s_parse_dt()
1058 				PTR_ERR(i2s->i2sclk));  in stm32_i2s_parse_dt()
1059 		return PTR_ERR(i2s->i2sclk);  in stm32_i2s_parse_dt()
1062 	i2s->x8kclk = devm_clk_get(&pdev->dev, "x8k");  in stm32_i2s_parse_dt()
1063 	if (IS_ERR(i2s->x8kclk)) {  in stm32_i2s_parse_dt()
1064 		if (PTR_ERR(i2s->x8kclk) != -EPROBE_DEFER)  in stm32_i2s_parse_dt()
1065 			dev_err(&pdev->dev, "Could not get x8k parent clock: %ld\n",  in stm32_i2s_parse_dt()
1066 				PTR_ERR(i2s->x8kclk));  in stm32_i2s_parse_dt()
1067 		return PTR_ERR(i2s->x8kclk);  in stm32_i2s_parse_dt()
1070 	i2s->x11kclk = devm_clk_get(&pdev->dev, "x11k");  in stm32_i2s_parse_dt()
1071 	if (IS_ERR(i2s->x11kclk)) {  in stm32_i2s_parse_dt()
1072 		if (PTR_ERR(i2s->x11kclk) != -EPROBE_DEFER)  in stm32_i2s_parse_dt()
1073 			dev_err(&pdev->dev, "Could not get x11k parent clock: %ld\n",  in stm32_i2s_parse_dt()
1074 				PTR_ERR(i2s->x11kclk));  in stm32_i2s_parse_dt()
1075 		return PTR_ERR(i2s->x11kclk);  in stm32_i2s_parse_dt()
1079 	if (of_find_property(np, "#clock-cells", NULL)) {  in stm32_i2s_parse_dt()
1090 	ret = devm_request_irq(&pdev->dev, irq, stm32_i2s_isr, IRQF_ONESHOT,  in stm32_i2s_parse_dt()
1091 			       dev_name(&pdev->dev), i2s);  in stm32_i2s_parse_dt()
1093 		dev_err(&pdev->dev, "irq request returned %d\n", ret);  in stm32_i2s_parse_dt()
1098 	rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);  in stm32_i2s_parse_dt()
1100 		if (PTR_ERR(rst) != -EPROBE_DEFER)  in stm32_i2s_parse_dt()
1101 			dev_err(&pdev->dev, "Reset controller error %ld\n",  in stm32_i2s_parse_dt()
1114 	snd_dmaengine_pcm_unregister(&pdev->dev);  in stm32_i2s_remove()
1115 	snd_soc_unregister_component(&pdev->dev);  in stm32_i2s_remove()
1126 	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);  in stm32_i2s_probe()
1128 		return -ENOMEM;  in stm32_i2s_probe()
1130 	i2s->pdev = pdev;  in stm32_i2s_probe()
1131 	i2s->ms_flg = I2S_MS_NOT_SET;  in stm32_i2s_probe()
1132 	spin_lock_init(&i2s->lock_fd);  in stm32_i2s_probe()
1133 	spin_lock_init(&i2s->irq_lock);  in stm32_i2s_probe()
1144 	i2s->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "pclk",  in stm32_i2s_probe()
1145 						i2s->base, i2s->regmap_conf);  in stm32_i2s_probe()
1146 	if (IS_ERR(i2s->regmap)) {  in stm32_i2s_probe()
1147 		if (PTR_ERR(i2s->regmap) != -EPROBE_DEFER)  in stm32_i2s_probe()
1148 			dev_err(&pdev->dev, "Regmap init error %ld\n",  in stm32_i2s_probe()
1149 				PTR_ERR(i2s->regmap));  in stm32_i2s_probe()
1150 		return PTR_ERR(i2s->regmap);  in stm32_i2s_probe()
1153 	ret = snd_dmaengine_pcm_register(&pdev->dev, &stm32_i2s_pcm_config, 0);  in stm32_i2s_probe()
1155 		if (ret != -EPROBE_DEFER)  in stm32_i2s_probe()
1156 			dev_err(&pdev->dev, "PCM DMA register error %d\n", ret);  in stm32_i2s_probe()
1160 	ret = snd_soc_register_component(&pdev->dev, &stm32_i2s_component,  in stm32_i2s_probe()
1161 					 i2s->dai_drv, 1);  in stm32_i2s_probe()
1163 		snd_dmaengine_pcm_unregister(&pdev->dev);  in stm32_i2s_probe()
1167 	/* Set SPI/I2S in i2s mode */  in stm32_i2s_probe()
1168 	ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,  in stm32_i2s_probe()
1173 	ret = regmap_read(i2s->regmap, STM32_I2S_IPIDR_REG, &val);  in stm32_i2s_probe()
1178 		ret = regmap_read(i2s->regmap, STM32_I2S_HWCFGR_REG, &val);  in stm32_i2s_probe()
1183 			dev_err(&pdev->dev,  in stm32_i2s_probe()
1185 			ret = -EPERM;  in stm32_i2s_probe()
1189 		ret = regmap_read(i2s->regmap, STM32_I2S_VERR_REG, &val);  in stm32_i2s_probe()
1193 		dev_dbg(&pdev->dev, "I2S version: %lu.%lu registered\n",  in stm32_i2s_probe()
1213 	regcache_cache_only(i2s->regmap, true);  in stm32_i2s_suspend()
1214 	regcache_mark_dirty(i2s->regmap);  in stm32_i2s_suspend()
1223 	regcache_cache_only(i2s->regmap, false);  in stm32_i2s_resume()
1224 	return regcache_sync(i2s->regmap);  in stm32_i2s_resume()
1234 		.name = "st,stm32-i2s",
1246 MODULE_ALIAS("platform:stm32-i2s");