Lines Matching refs:catpt_updatel_pci
158 catpt_updatel_pci(cdev, VDRTCTL0, mask, new); in catpt_dsp_set_srampge()
198 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0); in catpt_dsp_update_srampge()
203 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, in catpt_dsp_update_srampge()
236 catpt_updatel_pci(cdev, VDRTCTL0, LPT_VDRTCTL0_APLLSE, val); in lpt_dsp_pll_shutdown()
244 catpt_updatel_pci(cdev, VDRTCTL2, WPT_VDRTCTL2_APLLSE, val); in wpt_dsp_pll_shutdown()
352 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0); in catpt_dsp_power_down()
367 catpt_updatel_pci(cdev, VDRTCTL2, mask, val); in catpt_dsp_power_down()
369 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DTCGE, in catpt_dsp_power_down()
378 catpt_updatel_pci(cdev, VDRTCTL0, mask, cdev->spec->d3pgd_bit); in catpt_dsp_power_down()
380 catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D3hot); in catpt_dsp_power_down()
385 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, in catpt_dsp_power_down()
397 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0); in catpt_dsp_power_up()
402 catpt_updatel_pci(cdev, VDRTCTL2, mask, val); in catpt_dsp_power_up()
404 catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D0); in catpt_dsp_power_up()
408 catpt_updatel_pci(cdev, VDRTCTL0, mask, mask); in catpt_dsp_power_up()
423 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, in catpt_dsp_power_up()