Lines Matching +full:imx8mm +full:- +full:soc
1 // SPDX-License-Identifier: GPL-2.0
3 // Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
23 #include <sound/soc.h>
26 #include "imx-pcm.h"
47 * struct fsl_spdif_soc_data: soc specific data
94 * struct fsl_spdif_priv - Freescale SPDIF private data
95 * @soc: SPDIF soc data
110 * @spbaclk: SPBA clock (optional, depending on SoC design)
116 const struct fsl_spdif_soc_data *soc; member
192 return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock; in fsl_spdif_can_set_clk_rate()
198 struct regmap *regmap = spdif_priv->regmap; in spdif_irq_dpll_lock()
199 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_dpll_lock()
205 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n", in spdif_irq_dpll_lock()
208 spdif_priv->dpll_locked = locked ? true : false; in spdif_irq_dpll_lock()
214 struct regmap *regmap = spdif_priv->regmap; in spdif_irq_sym_error()
215 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_sym_error()
217 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n"); in spdif_irq_sym_error()
220 if (!spdif_priv->dpll_locked) in spdif_irq_sym_error()
227 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_irq_uqrx_full()
228 struct regmap *regmap = spdif_priv->regmap; in spdif_irq_uqrx_full()
229 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_uqrx_full()
234 pos = &ctrl->upos; in spdif_irq_uqrx_full()
239 pos = &ctrl->qpos; in spdif_irq_uqrx_full()
244 dev_err(&pdev->dev, "unsupported channel name\n"); in spdif_irq_uqrx_full()
248 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name); in spdif_irq_uqrx_full()
253 dev_err(&pdev->dev, "User bit receive buffer overflow\n"); in spdif_irq_uqrx_full()
258 ctrl->subcode[*pos++] = val >> 16; in spdif_irq_uqrx_full()
259 ctrl->subcode[*pos++] = val >> 8; in spdif_irq_uqrx_full()
260 ctrl->subcode[*pos++] = val; in spdif_irq_uqrx_full()
266 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_irq_uq_sync()
267 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_uq_sync()
269 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n"); in spdif_irq_uq_sync()
272 if (ctrl->qpos == 0) in spdif_irq_uq_sync()
276 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1; in spdif_irq_uq_sync()
282 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_irq_uq_err()
283 struct regmap *regmap = spdif_priv->regmap; in spdif_irq_uq_err()
284 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_uq_err()
287 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n"); in spdif_irq_uq_err()
294 ctrl->ready_buf = 0; in spdif_irq_uq_err()
295 ctrl->upos = 0; in spdif_irq_uq_err()
296 ctrl->qpos = 0; in spdif_irq_uq_err()
302 struct regmap *regmap = spdif_priv->regmap; in spdif_intr_status_clear()
316 struct platform_device *pdev = spdif_priv->pdev; in spdif_isr()
325 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n"); in spdif_isr()
328 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n"); in spdif_isr()
331 dev_dbg(&pdev->dev, "isr: cstatus new\n"); in spdif_isr()
334 dev_dbg(&pdev->dev, "isr: validity flag no good\n"); in spdif_isr()
340 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n"); in spdif_isr()
346 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n"); in spdif_isr()
352 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n"); in spdif_isr()
361 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n"); in spdif_isr()
364 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n"); in spdif_isr()
371 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n"); in spdif_isr()
375 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n"); in spdif_isr()
382 struct regmap *regmap = spdif_priv->regmap; in spdif_softreset()
395 } while ((val & SCR_SOFT_RESET) && cycle--); in spdif_softreset()
404 return -EBUSY; in spdif_softreset()
410 ctrl->ch_status[3] &= ~mask; in spdif_set_cstatus()
411 ctrl->ch_status[3] |= cstatus & mask; in spdif_set_cstatus()
416 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_write_channel_status()
417 struct regmap *regmap = spdif_priv->regmap; in spdif_write_channel_status()
418 struct platform_device *pdev = spdif_priv->pdev; in spdif_write_channel_status()
421 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) | in spdif_write_channel_status()
422 (bitrev8(ctrl->ch_status[1]) << 8) | in spdif_write_channel_status()
423 bitrev8(ctrl->ch_status[2]); in spdif_write_channel_status()
426 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status); in spdif_write_channel_status()
428 ch_status = bitrev8(ctrl->ch_status[3]) << 16; in spdif_write_channel_status()
431 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status); in spdif_write_channel_status()
438 struct regmap *regmap = spdif_priv->regmap; in spdif_set_rx_clksrc()
439 u8 clksrc = spdif_priv->rxclk_src; in spdif_set_rx_clksrc()
442 return -EINVAL; in spdif_set_rx_clksrc()
456 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_set_sample_rate()
457 struct regmap *regmap = spdif_priv->regmap; in spdif_set_sample_rate()
458 struct platform_device *pdev = spdif_priv->pdev; in spdif_set_sample_rate()
495 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate); in spdif_set_sample_rate()
496 return -EINVAL; in spdif_set_sample_rate()
499 clk = spdif_priv->txclk_src[rate]; in spdif_set_sample_rate()
501 dev_err(&pdev->dev, "tx clock source is out of range\n"); in spdif_set_sample_rate()
502 return -EINVAL; in spdif_set_sample_rate()
505 txclk_df = spdif_priv->txclk_df[rate]; in spdif_set_sample_rate()
507 dev_err(&pdev->dev, "the txclk_df can't be zero\n"); in spdif_set_sample_rate()
508 return -EINVAL; in spdif_set_sample_rate()
511 sysclk_df = spdif_priv->sysclk_df[rate]; in spdif_set_sample_rate()
517 ret = clk_set_rate(spdif_priv->txclk[rate], in spdif_set_sample_rate()
520 dev_err(&pdev->dev, "failed to set tx clock rate\n"); in spdif_set_sample_rate()
525 dev_dbg(&pdev->dev, "expected clock rate = %d\n", in spdif_set_sample_rate()
527 dev_dbg(&pdev->dev, "actual clock rate = %ld\n", in spdif_set_sample_rate()
528 clk_get_rate(spdif_priv->txclk[rate])); in spdif_set_sample_rate()
540 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n", in spdif_set_sample_rate()
541 spdif_priv->txrate[rate], sample_rate); in spdif_set_sample_rate()
551 struct platform_device *pdev = spdif_priv->pdev; in fsl_spdif_startup()
552 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_startup()
560 dev_err(&pdev->dev, "failed to soft reset\n"); in fsl_spdif_startup()
568 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in fsl_spdif_startup()
593 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_shutdown()
596 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in fsl_spdif_shutdown()
622 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_hw_params()
623 struct platform_device *pdev = spdif_priv->pdev; in fsl_spdif_hw_params()
627 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in fsl_spdif_hw_params()
630 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n", in fsl_spdif_hw_params()
650 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_trigger()
651 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_spdif_trigger()
669 return -EINVAL; in fsl_spdif_trigger()
696 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; in fsl_spdif_info()
697 uinfo->count = 1; in fsl_spdif_info()
707 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_pb_get()
709 uvalue->value.iec958.status[0] = ctrl->ch_status[0]; in fsl_spdif_pb_get()
710 uvalue->value.iec958.status[1] = ctrl->ch_status[1]; in fsl_spdif_pb_get()
711 uvalue->value.iec958.status[2] = ctrl->ch_status[2]; in fsl_spdif_pb_get()
712 uvalue->value.iec958.status[3] = ctrl->ch_status[3]; in fsl_spdif_pb_get()
722 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_pb_put()
724 ctrl->ch_status[0] = uvalue->value.iec958.status[0]; in fsl_spdif_pb_put()
725 ctrl->ch_status[1] = uvalue->value.iec958.status[1]; in fsl_spdif_pb_put()
726 ctrl->ch_status[2] = uvalue->value.iec958.status[2]; in fsl_spdif_pb_put()
727 ctrl->ch_status[3] = uvalue->value.iec958.status[3]; in fsl_spdif_pb_put()
740 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_capture_get()
745 return -EAGAIN; in fsl_spdif_capture_get()
748 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF; in fsl_spdif_capture_get()
749 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF; in fsl_spdif_capture_get()
750 ucontrol->value.iec958.status[2] = cstatus & 0xFF; in fsl_spdif_capture_get()
753 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF; in fsl_spdif_capture_get()
754 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF; in fsl_spdif_capture_get()
755 ucontrol->value.iec958.status[5] = cstatus & 0xFF; in fsl_spdif_capture_get()
772 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_subcode_get()
774 int ret = -EAGAIN; in fsl_spdif_subcode_get()
776 spin_lock_irqsave(&ctrl->ctl_lock, flags); in fsl_spdif_subcode_get()
777 if (ctrl->ready_buf) { in fsl_spdif_subcode_get()
778 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE; in fsl_spdif_subcode_get()
779 memcpy(&ucontrol->value.iec958.subcode[0], in fsl_spdif_subcode_get()
780 &ctrl->subcode[idx], SPDIF_UBITS_SIZE); in fsl_spdif_subcode_get()
783 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); in fsl_spdif_subcode_get()
788 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */
792 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; in fsl_spdif_qinfo()
793 uinfo->count = SPDIF_QSUB_SIZE; in fsl_spdif_qinfo()
804 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_qget()
806 int ret = -EAGAIN; in fsl_spdif_qget()
808 spin_lock_irqsave(&ctrl->ctl_lock, flags); in fsl_spdif_qget()
809 if (ctrl->ready_buf) { in fsl_spdif_qget()
810 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE; in fsl_spdif_qget()
811 memcpy(&ucontrol->value.bytes.data[0], in fsl_spdif_qget()
812 &ctrl->qsub[idx], SPDIF_QSUB_SIZE); in fsl_spdif_qget()
815 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); in fsl_spdif_qget()
826 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_rx_vbit_get()
830 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0; in fsl_spdif_rx_vbit_get()
841 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_tx_vbit_get()
846 val = 1 - val; in fsl_spdif_tx_vbit_get()
847 ucontrol->value.integer.value[0] = val; in fsl_spdif_tx_vbit_get()
857 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_tx_vbit_put()
858 u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET; in fsl_spdif_tx_vbit_put()
870 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_rx_rcm_get()
875 ucontrol->value.integer.value[0] = val; in fsl_spdif_rx_rcm_get()
885 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_rx_rcm_put()
886 u32 val = (ucontrol->value.integer.value[0] ? SCR_RAW_CAPTURE_MODE : 0); in fsl_spdif_rx_rcm_put()
889 cpu_dai->driver->capture.formats |= SNDRV_PCM_FMTBIT_S32_LE; in fsl_spdif_rx_rcm_put()
891 cpu_dai->driver->capture.formats &= ~SNDRV_PCM_FMTBIT_S32_LE; in fsl_spdif_rx_rcm_put()
902 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; in fsl_spdif_rxrate_info()
903 uinfo->count = 1; in fsl_spdif_rxrate_info()
904 uinfo->value.integer.min = 16000; in fsl_spdif_rxrate_info()
905 uinfo->value.integer.max = 192000; in fsl_spdif_rxrate_info()
918 struct regmap *regmap = spdif_priv->regmap; in spdif_get_rxclk_rate()
919 struct platform_device *pdev = spdif_priv->pdev; in spdif_get_rxclk_rate()
931 busclk_freq = clk_get_rate(spdif_priv->sysclk); in spdif_get_rxclk_rate()
938 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas); in spdif_get_rxclk_rate()
939 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq); in spdif_get_rxclk_rate()
940 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64); in spdif_get_rxclk_rate()
957 if (spdif_priv->dpll_locked) in fsl_spdif_rxrate_get()
960 ucontrol->value.integer.value[0] = rate; in fsl_spdif_rxrate_get()
968 * 0 Non-CD data
975 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_usync_get()
979 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0; in fsl_spdif_usync_get()
987 * 0 Non-CD data
994 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_usync_put()
995 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET; in fsl_spdif_usync_put()
1034 .name = "IEC958 Q-subcode Capture Default",
1043 .name = "IEC958 RX V-Bit Errors",
1051 .name = "IEC958 TX V-Bit",
1098 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx, in fsl_spdif_dai_probe()
1099 &spdif_private->dma_params_rx); in fsl_spdif_dai_probe()
1103 if (spdif_private->soc->raw_capture_mode) in fsl_spdif_dai_probe()
1108 regmap_update_bits(spdif_private->regmap, REG_SPDIF_SCR, in fsl_spdif_dai_probe()
1117 .stream_name = "CPU-Playback",
1124 .stream_name = "CPU-Capture",
1134 .name = "fsl-spdif",
1230 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk); in fsl_spdif_txclk_caldiv()
1254 spdif_priv->txclk_df[index] = txclk_df; in fsl_spdif_txclk_caldiv()
1255 spdif_priv->sysclk_df[index] = sysclk_df; in fsl_spdif_txclk_caldiv()
1256 spdif_priv->txrate[index] = arate; in fsl_spdif_txclk_caldiv()
1260 sub = (u64)(arate - rate[index]) * 100000; in fsl_spdif_txclk_caldiv()
1265 spdif_priv->txclk_df[index] = txclk_df; in fsl_spdif_txclk_caldiv()
1266 spdif_priv->sysclk_df[index] = sysclk_df; in fsl_spdif_txclk_caldiv()
1267 spdif_priv->txrate[index] = arate; in fsl_spdif_txclk_caldiv()
1270 sub = (u64)(rate[index] - arate) * 100000; in fsl_spdif_txclk_caldiv()
1275 spdif_priv->txclk_df[index] = txclk_df; in fsl_spdif_txclk_caldiv()
1276 spdif_priv->sysclk_df[index] = sysclk_df; in fsl_spdif_txclk_caldiv()
1277 spdif_priv->txrate[index] = arate; in fsl_spdif_txclk_caldiv()
1291 struct platform_device *pdev = spdif_priv->pdev; in fsl_spdif_probe_txclk()
1292 struct device *dev = &pdev->dev; in fsl_spdif_probe_txclk()
1314 spdif_priv->txclk[index] = clk; in fsl_spdif_probe_txclk()
1315 spdif_priv->txclk_src[index] = i; in fsl_spdif_probe_txclk()
1323 spdif_priv->txclk_src[index], rate[index]); in fsl_spdif_probe_txclk()
1325 spdif_priv->txclk_df[index], rate[index]); in fsl_spdif_probe_txclk()
1326 if (clk_is_match(spdif_priv->txclk[index], spdif_priv->sysclk)) in fsl_spdif_probe_txclk()
1328 spdif_priv->sysclk_df[index], rate[index]); in fsl_spdif_probe_txclk()
1330 rate[index], spdif_priv->txrate[index]); in fsl_spdif_probe_txclk()
1343 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL); in fsl_spdif_probe()
1345 return -ENOMEM; in fsl_spdif_probe()
1347 spdif_priv->pdev = pdev; in fsl_spdif_probe()
1349 spdif_priv->soc = of_device_get_match_data(&pdev->dev); in fsl_spdif_probe()
1352 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai)); in fsl_spdif_probe()
1353 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev); in fsl_spdif_probe()
1354 spdif_priv->cpu_dai_drv.playback.formats = in fsl_spdif_probe()
1355 spdif_priv->soc->tx_formats; in fsl_spdif_probe()
1362 spdif_priv->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_spdif_regmap_config); in fsl_spdif_probe()
1363 if (IS_ERR(spdif_priv->regmap)) { in fsl_spdif_probe()
1364 dev_err(&pdev->dev, "regmap init failed\n"); in fsl_spdif_probe()
1365 return PTR_ERR(spdif_priv->regmap); in fsl_spdif_probe()
1368 for (i = 0; i < spdif_priv->soc->interrupts; i++) { in fsl_spdif_probe()
1373 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0, in fsl_spdif_probe()
1374 dev_name(&pdev->dev), spdif_priv); in fsl_spdif_probe()
1376 dev_err(&pdev->dev, "could not claim irq %u\n", irq); in fsl_spdif_probe()
1382 spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5"); in fsl_spdif_probe()
1383 if (IS_ERR(spdif_priv->sysclk)) { in fsl_spdif_probe()
1384 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n"); in fsl_spdif_probe()
1385 return PTR_ERR(spdif_priv->sysclk); in fsl_spdif_probe()
1389 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); in fsl_spdif_probe()
1390 if (IS_ERR(spdif_priv->coreclk)) { in fsl_spdif_probe()
1391 dev_err(&pdev->dev, "no core clock in devicetree\n"); in fsl_spdif_probe()
1392 return PTR_ERR(spdif_priv->coreclk); in fsl_spdif_probe()
1395 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba"); in fsl_spdif_probe()
1396 if (IS_ERR(spdif_priv->spbaclk)) in fsl_spdif_probe()
1397 dev_warn(&pdev->dev, "no spba clock in devicetree\n"); in fsl_spdif_probe()
1400 spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1"); in fsl_spdif_probe()
1401 if (IS_ERR(spdif_priv->rxclk)) { in fsl_spdif_probe()
1402 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n"); in fsl_spdif_probe()
1403 return PTR_ERR(spdif_priv->rxclk); in fsl_spdif_probe()
1405 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC; in fsl_spdif_probe()
1414 ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_probe()
1415 spin_lock_init(&ctrl->ctl_lock); in fsl_spdif_probe()
1418 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT | in fsl_spdif_probe()
1420 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID; in fsl_spdif_probe()
1421 ctrl->ch_status[2] = 0x00; in fsl_spdif_probe()
1422 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 | in fsl_spdif_probe()
1425 spdif_priv->dpll_locked = false; in fsl_spdif_probe()
1427 spdif_priv->dma_params_tx.maxburst = spdif_priv->soc->tx_burst; in fsl_spdif_probe()
1428 spdif_priv->dma_params_rx.maxburst = spdif_priv->soc->rx_burst; in fsl_spdif_probe()
1429 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL; in fsl_spdif_probe()
1430 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL; in fsl_spdif_probe()
1433 dev_set_drvdata(&pdev->dev, spdif_priv); in fsl_spdif_probe()
1434 pm_runtime_enable(&pdev->dev); in fsl_spdif_probe()
1435 regcache_cache_only(spdif_priv->regmap, true); in fsl_spdif_probe()
1443 dev_err_probe(&pdev->dev, ret, "imx_pcm_dma_init failed\n"); in fsl_spdif_probe()
1447 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component, in fsl_spdif_probe()
1448 &spdif_priv->cpu_dai_drv, 1); in fsl_spdif_probe()
1450 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); in fsl_spdif_probe()
1457 pm_runtime_disable(&pdev->dev); in fsl_spdif_probe()
1463 pm_runtime_disable(&pdev->dev); in fsl_spdif_remove()
1475 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SIE, 0xffffff, 0); in fsl_spdif_runtime_suspend()
1477 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC, in fsl_spdif_runtime_suspend()
1478 &spdif_priv->regcache_srpc); in fsl_spdif_runtime_suspend()
1479 regcache_cache_only(spdif_priv->regmap, true); in fsl_spdif_runtime_suspend()
1481 clk_disable_unprepare(spdif_priv->rxclk); in fsl_spdif_runtime_suspend()
1484 clk_disable_unprepare(spdif_priv->txclk[i]); in fsl_spdif_runtime_suspend()
1486 if (!IS_ERR(spdif_priv->spbaclk)) in fsl_spdif_runtime_suspend()
1487 clk_disable_unprepare(spdif_priv->spbaclk); in fsl_spdif_runtime_suspend()
1488 clk_disable_unprepare(spdif_priv->coreclk); in fsl_spdif_runtime_suspend()
1499 ret = clk_prepare_enable(spdif_priv->coreclk); in fsl_spdif_runtime_resume()
1505 if (!IS_ERR(spdif_priv->spbaclk)) { in fsl_spdif_runtime_resume()
1506 ret = clk_prepare_enable(spdif_priv->spbaclk); in fsl_spdif_runtime_resume()
1514 ret = clk_prepare_enable(spdif_priv->txclk[i]); in fsl_spdif_runtime_resume()
1519 ret = clk_prepare_enable(spdif_priv->rxclk); in fsl_spdif_runtime_resume()
1523 regcache_cache_only(spdif_priv->regmap, false); in fsl_spdif_runtime_resume()
1524 regcache_mark_dirty(spdif_priv->regmap); in fsl_spdif_runtime_resume()
1526 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC, in fsl_spdif_runtime_resume()
1528 spdif_priv->regcache_srpc); in fsl_spdif_runtime_resume()
1530 ret = regcache_sync(spdif_priv->regmap); in fsl_spdif_runtime_resume()
1537 clk_disable_unprepare(spdif_priv->rxclk); in fsl_spdif_runtime_resume()
1539 for (i--; i >= 0; i--) in fsl_spdif_runtime_resume()
1540 clk_disable_unprepare(spdif_priv->txclk[i]); in fsl_spdif_runtime_resume()
1541 if (!IS_ERR(spdif_priv->spbaclk)) in fsl_spdif_runtime_resume()
1542 clk_disable_unprepare(spdif_priv->spbaclk); in fsl_spdif_runtime_resume()
1544 clk_disable_unprepare(spdif_priv->coreclk); in fsl_spdif_runtime_resume()
1558 { .compatible = "fsl,imx35-spdif", .data = &fsl_spdif_imx35, },
1559 { .compatible = "fsl,vf610-spdif", .data = &fsl_spdif_vf610, },
1560 { .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, },
1561 { .compatible = "fsl,imx8qm-spdif", .data = &fsl_spdif_imx8qm, },
1562 { .compatible = "fsl,imx8mm-spdif", .data = &fsl_spdif_imx8mm, },
1569 .name = "fsl-spdif-dai",
1582 MODULE_ALIAS("platform:fsl-spdif-dai");