Lines Matching +full:imx8mm +full:- +full:soc
1 // SPDX-License-Identifier: GPL-2.0
20 #include <sound/soc.h>
25 #include "imx-pcm.h"
33 const struct fsl_micfil_soc_data *soc; member
41 int quality; /*QUALITY 2-0 bits */
61 { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
118 regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg); in get_pdm_clk()
119 osr = 16 - ((ctrl2_reg & MICFIL_CTRL2_CICOSR_MASK) in get_pdm_clk()
122 regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg); in get_pdm_clk()
141 dev_err(&micfil->pdev->dev, in get_pdm_clk()
143 bclk = -1; in get_pdm_clk()
157 regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg); in get_clk_div()
159 mclk_rate = clk_get_rate(micfil->mclk); in get_clk_div()
166 /* The SRES is a self-negated bit which provides the CPU with the
168 * slave-bus interface. This bit always reads as zero, and this
176 ret = regmap_update_bits(micfil->regmap, in fsl_micfil_reset()
185 ret = regmap_update_bits(micfil->regmap, in fsl_micfil_reset()
200 struct device *dev = &micfil->pdev->dev; in fsl_micfil_set_mclk_rate()
203 clk_disable_unprepare(micfil->mclk); in fsl_micfil_set_mclk_rate()
205 ret = clk_set_rate(micfil->mclk, freq * 1024); in fsl_micfil_set_mclk_rate()
210 clk_prepare_enable(micfil->mclk); in fsl_micfil_set_mclk_rate()
221 dev_err(dai->dev, "micfil dai priv_data not set\n"); in fsl_micfil_startup()
222 return -EINVAL; in fsl_micfil_startup()
232 struct device *dev = &micfil->pdev->dev; in fsl_micfil_trigger()
245 /* DMA Interrupt Selection - DISEL bits in fsl_micfil_trigger()
246 * 00 - DMA and IRQ disabled in fsl_micfil_trigger()
247 * 01 - DMA req enabled in fsl_micfil_trigger()
248 * 10 - IRQ enabled in fsl_micfil_trigger()
249 * 11 - reserved in fsl_micfil_trigger()
251 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, in fsl_micfil_trigger()
260 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, in fsl_micfil_trigger()
273 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, in fsl_micfil_trigger()
281 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, in fsl_micfil_trigger()
290 return -EINVAL; in fsl_micfil_trigger()
304 clk_get_rate(micfil->mclk), rate); in fsl_set_clock_params()
307 ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, in fsl_set_clock_params()
317 ret = -EINVAL; in fsl_set_clock_params()
319 ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, in fsl_set_clock_params()
335 struct device *dev = &micfil->pdev->dev; in fsl_micfil_hw_params()
339 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, in fsl_micfil_hw_params()
347 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, in fsl_micfil_hw_params()
348 0xFF, ((1 << channels) - 1)); in fsl_micfil_hw_params()
361 micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX; in fsl_micfil_hw_params()
370 struct device *dev = &micfil->pdev->dev; in fsl_micfil_set_dai_sysclk()
380 clk_get_rate(micfil->mclk), freq); in fsl_micfil_set_dai_sysclk()
394 struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev); in fsl_micfil_dai_probe()
395 struct device *dev = cpu_dai->dev; in fsl_micfil_dai_probe()
401 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, in fsl_micfil_dai_probe()
410 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777); in fsl_micfil_dai_probe()
412 micfil->channel_gain[i] = 0xF; in fsl_micfil_dai_probe()
415 &micfil->dma_params_rx); in fsl_micfil_dai_probe()
417 /* FIFO Watermark Control - FIFOWMK*/ in fsl_micfil_dai_probe()
418 val = MICFIL_FIFO_CTRL_FIFOWMK(micfil->soc->fifo_depth) - 1; in fsl_micfil_dai_probe()
419 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL, in fsl_micfil_dai_probe()
433 .stream_name = "CPU-Capture",
443 .name = "fsl-micfil-dai",
570 struct platform_device *pdev = micfil->pdev; in micfil_isr()
577 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg); in micfil_isr()
578 regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg); in micfil_isr()
579 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg); in micfil_isr()
583 /* Channel 0-7 Output Data Flags */ in micfil_isr()
586 dev_dbg(&pdev->dev, in micfil_isr()
592 regmap_write_bits(micfil->regmap, in micfil_isr()
600 dev_dbg(&pdev->dev, in micfil_isr()
605 dev_dbg(&pdev->dev, in micfil_isr()
616 struct platform_device *pdev = micfil->pdev; in micfil_err_isr()
619 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg); in micfil_err_isr()
622 dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n"); in micfil_err_isr()
625 dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n"); in micfil_err_isr()
628 dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n"); in micfil_err_isr()
629 regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, in micfil_err_isr()
638 struct device_node *np = pdev->dev.of_node; in fsl_micfil_probe()
645 micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL); in fsl_micfil_probe()
647 return -ENOMEM; in fsl_micfil_probe()
649 micfil->pdev = pdev; in fsl_micfil_probe()
650 strncpy(micfil->name, np->name, sizeof(micfil->name) - 1); in fsl_micfil_probe()
652 micfil->soc = of_device_get_match_data(&pdev->dev); in fsl_micfil_probe()
657 micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app"); in fsl_micfil_probe()
658 if (IS_ERR(micfil->mclk)) { in fsl_micfil_probe()
659 dev_err(&pdev->dev, "failed to get core clock: %ld\n", in fsl_micfil_probe()
660 PTR_ERR(micfil->mclk)); in fsl_micfil_probe()
661 return PTR_ERR(micfil->mclk); in fsl_micfil_probe()
664 micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk"); in fsl_micfil_probe()
665 if (IS_ERR(micfil->busclk)) { in fsl_micfil_probe()
666 dev_err(&pdev->dev, "failed to get ipg clock: %ld\n", in fsl_micfil_probe()
667 PTR_ERR(micfil->busclk)); in fsl_micfil_probe()
668 return PTR_ERR(micfil->busclk); in fsl_micfil_probe()
676 micfil->regmap = devm_regmap_init_mmio(&pdev->dev, in fsl_micfil_probe()
679 if (IS_ERR(micfil->regmap)) { in fsl_micfil_probe()
680 dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n", in fsl_micfil_probe()
681 PTR_ERR(micfil->regmap)); in fsl_micfil_probe()
682 return PTR_ERR(micfil->regmap); in fsl_micfil_probe()
689 &micfil->dataline); in fsl_micfil_probe()
691 micfil->dataline = 1; in fsl_micfil_probe()
693 if (micfil->dataline & ~micfil->soc->dataline) { in fsl_micfil_probe()
694 dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n", in fsl_micfil_probe()
695 micfil->soc->dataline); in fsl_micfil_probe()
696 return -EINVAL; in fsl_micfil_probe()
701 micfil->irq[i] = platform_get_irq(pdev, i); in fsl_micfil_probe()
702 dev_err(&pdev->dev, "GET IRQ: %d\n", micfil->irq[i]); in fsl_micfil_probe()
703 if (micfil->irq[i] < 0) in fsl_micfil_probe()
704 return micfil->irq[i]; in fsl_micfil_probe()
707 if (of_property_read_bool(np, "fsl,shared-interrupt")) in fsl_micfil_probe()
711 ret = devm_request_irq(&pdev->dev, micfil->irq[0], in fsl_micfil_probe()
713 micfil->name, micfil); in fsl_micfil_probe()
715 dev_err(&pdev->dev, "failed to claim mic interface irq %u\n", in fsl_micfil_probe()
716 micfil->irq[0]); in fsl_micfil_probe()
721 ret = devm_request_irq(&pdev->dev, micfil->irq[1], in fsl_micfil_probe()
723 micfil->name, micfil); in fsl_micfil_probe()
725 dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n", in fsl_micfil_probe()
726 micfil->irq[1]); in fsl_micfil_probe()
730 micfil->dma_params_rx.chan_name = "rx"; in fsl_micfil_probe()
731 micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0; in fsl_micfil_probe()
732 micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX; in fsl_micfil_probe()
737 pm_runtime_enable(&pdev->dev); in fsl_micfil_probe()
738 regcache_cache_only(micfil->regmap, true); in fsl_micfil_probe()
744 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); in fsl_micfil_probe()
746 dev_err(&pdev->dev, "failed to pcm register\n"); in fsl_micfil_probe()
750 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component, in fsl_micfil_probe()
753 dev_err(&pdev->dev, "failed to register component %s\n", in fsl_micfil_probe()
764 regcache_cache_only(micfil->regmap, true); in fsl_micfil_runtime_suspend()
766 clk_disable_unprepare(micfil->mclk); in fsl_micfil_runtime_suspend()
767 clk_disable_unprepare(micfil->busclk); in fsl_micfil_runtime_suspend()
777 ret = clk_prepare_enable(micfil->busclk); in fsl_micfil_runtime_resume()
781 ret = clk_prepare_enable(micfil->mclk); in fsl_micfil_runtime_resume()
783 clk_disable_unprepare(micfil->busclk); in fsl_micfil_runtime_resume()
787 regcache_cache_only(micfil->regmap, false); in fsl_micfil_runtime_resume()
788 regcache_mark_dirty(micfil->regmap); in fsl_micfil_runtime_resume()
789 regcache_sync(micfil->regmap); in fsl_micfil_runtime_resume()
819 .name = "fsl-micfil-dai",
826 MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>");