48 	{ ADCX140_PAGE_SELECT, 0x00 },
49 	{ ADCX140_SW_RESET, 0x00 },
50 	{ ADCX140_SLEEP_CFG, 0x00 },
51 	{ ADCX140_SHDN_CFG, 0x05 },
52 	{ ADCX140_ASI_CFG0, 0x30 },
53 	{ ADCX140_ASI_CFG1, 0x00 },
54 	{ ADCX140_ASI_CFG2, 0x00 },
55 	{ ADCX140_ASI_CH1, 0x00 },
56 	{ ADCX140_ASI_CH2, 0x01 },
57 	{ ADCX140_ASI_CH3, 0x02 },
58 	{ ADCX140_ASI_CH4, 0x03 },
59 	{ ADCX140_ASI_CH5, 0x04 },
60 	{ ADCX140_ASI_CH6, 0x05 },
61 	{ ADCX140_ASI_CH7, 0x06 },
62 	{ ADCX140_ASI_CH8, 0x07 },
63 	{ ADCX140_MST_CFG0, 0x02 },
64 	{ ADCX140_MST_CFG1, 0x48 },
65 	{ ADCX140_ASI_STS, 0xff },
66 	{ ADCX140_CLK_SRC, 0x10 },
67 	{ ADCX140_PDMCLK_CFG, 0x40 },
68 	{ ADCX140_PDM_CFG, 0x00 },
69 	{ ADCX140_GPIO_CFG0, 0x22 },
70 	{ ADCX140_GPO_CFG0, 0x00 },
71 	{ ADCX140_GPO_CFG1, 0x00 },
72 	{ ADCX140_GPO_CFG2, 0x00 },
73 	{ ADCX140_GPO_CFG3, 0x00 },
74 	{ ADCX140_GPO_VAL, 0x00 },
75 	{ ADCX140_GPIO_MON, 0x00 },
76 	{ ADCX140_GPI_CFG0, 0x00 },
77 	{ ADCX140_GPI_CFG1, 0x00 },
78 	{ ADCX140_GPI_MON, 0x00 },
79 	{ ADCX140_INT_CFG, 0x00 },
80 	{ ADCX140_INT_MASK0, 0xff },
81 	{ ADCX140_INT_LTCH0, 0x00 },
82 	{ ADCX140_BIAS_CFG, 0x00 },
83 	{ ADCX140_CH1_CFG0, 0x00 },
84 	{ ADCX140_CH1_CFG1, 0x00 },
85 	{ ADCX140_CH1_CFG2, 0xc9 },
86 	{ ADCX140_CH1_CFG3, 0x80 },
87 	{ ADCX140_CH1_CFG4, 0x00 },
88 	{ ADCX140_CH2_CFG0, 0x00 },
89 	{ ADCX140_CH2_CFG1, 0x00 },
90 	{ ADCX140_CH2_CFG2, 0xc9 },
91 	{ ADCX140_CH2_CFG3, 0x80 },
92 	{ ADCX140_CH2_CFG4, 0x00 },
93 	{ ADCX140_CH3_CFG0, 0x00 },
94 	{ ADCX140_CH3_CFG1, 0x00 },
95 	{ ADCX140_CH3_CFG2, 0xc9 },
96 	{ ADCX140_CH3_CFG3, 0x80 },
97 	{ ADCX140_CH3_CFG4, 0x00 },
98 	{ ADCX140_CH4_CFG0, 0x00 },
99 	{ ADCX140_CH4_CFG1, 0x00 },
100 	{ ADCX140_CH4_CFG2, 0xc9 },
101 	{ ADCX140_CH4_CFG3, 0x80 },
102 	{ ADCX140_CH4_CFG4, 0x00 },
103 	{ ADCX140_CH5_CFG2, 0xc9 },
104 	{ ADCX140_CH5_CFG3, 0x80 },
105 	{ ADCX140_CH5_CFG4, 0x00 },
106 	{ ADCX140_CH6_CFG2, 0xc9 },
107 	{ ADCX140_CH6_CFG3, 0x80 },
108 	{ ADCX140_CH6_CFG4, 0x00 },
109 	{ ADCX140_CH7_CFG2, 0xc9 },
110 	{ ADCX140_CH7_CFG3, 0x80 },
111 	{ ADCX140_CH7_CFG4, 0x00 },
112 	{ ADCX140_CH8_CFG2, 0xc9 },
113 	{ ADCX140_CH8_CFG3, 0x80 },
114 	{ ADCX140_CH8_CFG4, 0x00 },
115 	{ ADCX140_DSP_CFG0, 0x01 },
116 	{ ADCX140_DSP_CFG1, 0x40 },
117 	{ ADCX140_DRE_CFG0, 0x7b },
118 	{ ADCX140_AGC_CFG0, 0xe7 },
119 	{ ADCX140_IN_CH_EN, 0xf0 },
120 	{ ADCX140_ASI_OUT_CH_EN, 0x00 },
121 	{ ADCX140_PWR_CFG, 0x00 },
122 	{ ADCX140_DEV_STS0, 0x00 },
123 	{ ADCX140_DEV_STS1, 0x80 },
128 		.range_min = 0,
131 		.selector_mask = 0xff,
132 		.selector_shift = 0,
133 		.window_start = 0,
164 static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10050, 50, 0);
166 /* ADC gain. From 0 to 42 dB in 1 dB steps */
167 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 100, 0);
170 static DECLARE_TLV_DB_SCALE(dre_thresh_tlv, -6600, 100, 0);
172 static DECLARE_TLV_DB_SCALE(dre_gain_tlv, 200, 200, 0);
175 static DECLARE_TLV_DB_SCALE(agc_thresh_tlv, -3600, 200, 0);
177 static DECLARE_TLV_DB_SCALE(agc_gain_tlv, 300, 300, 0);
194 static SOC_ENUM_SINGLE_DECL(pdmclk_select_enum, ADCX140_PDMCLK_CFG, 0,
316 	SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 7, 1, 0);
318 	SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 6, 1, 0);
320 	SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 5, 1, 0);
322 	SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 4, 1, 0);
324 	SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 3, 1, 0);
326 	SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 2, 1, 0);
328 	SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 1, 1, 0);
330 	SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 0, 1, 0);
333 	SOC_DAPM_SINGLE("Switch", ADCX140_CH1_CFG0, 0, 1, 0);
335 	SOC_DAPM_SINGLE("Switch", ADCX140_CH2_CFG0, 0, 1, 0);
337 	SOC_DAPM_SINGLE("Switch", ADCX140_CH3_CFG0, 0, 1, 0);
339 	SOC_DAPM_SINGLE("Switch", ADCX140_CH4_CFG0, 0, 1, 0);
342 	SOC_DAPM_SINGLE("Switch", ADCX140_DSP_CFG1, 3, 1, 0);
346 	SOC_DAPM_SINGLE("Digital CH1 Switch", 0, 0, 0, 0),
347 	SOC_DAPM_SINGLE("Digital CH2 Switch", 0, 0, 0, 0),
348 	SOC_DAPM_SINGLE("Digital CH3 Switch", 0, 0, 0, 0),
349 	SOC_DAPM_SINGLE("Digital CH4 Switch", 0, 0, 0, 0),
372 	SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0,
373 		&adcx140_output_mixer_controls[0],
377 	SND_SOC_DAPM_MUX("MIC1P Input Mux", SND_SOC_NOPM, 0, 0,
379 	SND_SOC_DAPM_MUX("MIC2P Input Mux", SND_SOC_NOPM, 0, 0,
381 	SND_SOC_DAPM_MUX("MIC3P Input Mux", SND_SOC_NOPM, 0, 0,
383 	SND_SOC_DAPM_MUX("MIC4P Input Mux", SND_SOC_NOPM, 0, 0,
387 	SND_SOC_DAPM_MUX("MIC1 Analog Mux", SND_SOC_NOPM, 0, 0,
389 	SND_SOC_DAPM_MUX("MIC2 Analog Mux", SND_SOC_NOPM, 0, 0,
391 	SND_SOC_DAPM_MUX("MIC3 Analog Mux", SND_SOC_NOPM, 0, 0,
393 	SND_SOC_DAPM_MUX("MIC4 Analog Mux", SND_SOC_NOPM, 0, 0,
396 	SND_SOC_DAPM_MUX("MIC1M Input Mux", SND_SOC_NOPM, 0, 0,
398 	SND_SOC_DAPM_MUX("MIC2M Input Mux", SND_SOC_NOPM, 0, 0,
400 	SND_SOC_DAPM_MUX("MIC3M Input Mux", SND_SOC_NOPM, 0, 0,
402 	SND_SOC_DAPM_MUX("MIC4M Input Mux", SND_SOC_NOPM, 0, 0,
405 	SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH1", SND_SOC_NOPM, 0, 0, NULL, 0),
406 	SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH2", SND_SOC_NOPM, 0, 0, NULL, 0),
407 	SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH3", SND_SOC_NOPM, 0, 0, NULL, 0),
408 	SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH4", SND_SOC_NOPM, 0, 0, NULL, 0),
410 	SND_SOC_DAPM_ADC("CH1_ADC", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0),
411 	SND_SOC_DAPM_ADC("CH2_ADC", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0),
412 	SND_SOC_DAPM_ADC("CH3_ADC", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0),
413 	SND_SOC_DAPM_ADC("CH4_ADC", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0),
415 	SND_SOC_DAPM_ADC("CH1_DIG", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0),
416 	SND_SOC_DAPM_ADC("CH2_DIG", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0),
417 	SND_SOC_DAPM_ADC("CH3_DIG", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0),
418 	SND_SOC_DAPM_ADC("CH4_DIG", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0),
419 	SND_SOC_DAPM_ADC("CH5_DIG", "CH5 Capture", ADCX140_IN_CH_EN, 3, 0),
420 	SND_SOC_DAPM_ADC("CH6_DIG", "CH6 Capture", ADCX140_IN_CH_EN, 2, 0),
421 	SND_SOC_DAPM_ADC("CH7_DIG", "CH7 Capture", ADCX140_IN_CH_EN, 1, 0),
422 	SND_SOC_DAPM_ADC("CH8_DIG", "CH8 Capture", ADCX140_IN_CH_EN, 0, 0),
425 	SND_SOC_DAPM_SWITCH("CH1_ASI_EN", SND_SOC_NOPM, 0, 0,
427 	SND_SOC_DAPM_SWITCH("CH2_ASI_EN", SND_SOC_NOPM, 0, 0,
429 	SND_SOC_DAPM_SWITCH("CH3_ASI_EN", SND_SOC_NOPM, 0, 0,
431 	SND_SOC_DAPM_SWITCH("CH4_ASI_EN", SND_SOC_NOPM, 0, 0,
434 	SND_SOC_DAPM_SWITCH("CH5_ASI_EN", SND_SOC_NOPM, 0, 0,
436 	SND_SOC_DAPM_SWITCH("CH6_ASI_EN", SND_SOC_NOPM, 0, 0,
438 	SND_SOC_DAPM_SWITCH("CH7_ASI_EN", SND_SOC_NOPM, 0, 0,
440 	SND_SOC_DAPM_SWITCH("CH8_ASI_EN", SND_SOC_NOPM, 0, 0,
443 	SND_SOC_DAPM_SWITCH("DRE_ENABLE", SND_SOC_NOPM, 0, 0,
446 	SND_SOC_DAPM_SWITCH("CH1_DRE_EN", SND_SOC_NOPM, 0, 0,
448 	SND_SOC_DAPM_SWITCH("CH2_DRE_EN", SND_SOC_NOPM, 0, 0,
450 	SND_SOC_DAPM_SWITCH("CH3_DRE_EN", SND_SOC_NOPM, 0, 0,
452 	SND_SOC_DAPM_SWITCH("CH4_DRE_EN", SND_SOC_NOPM, 0, 0,
455 	SND_SOC_DAPM_MUX("IN1 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
457 	SND_SOC_DAPM_MUX("IN2 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
459 	SND_SOC_DAPM_MUX("IN3 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
461 	SND_SOC_DAPM_MUX("IN4 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
464 	SND_SOC_DAPM_MUX("PDM Clk Div Select", SND_SOC_NOPM, 0, 0,
467 	SND_SOC_DAPM_MUX("Decimation Filter", SND_SOC_NOPM, 0, 0,
597 	SOC_SINGLE_TLV("Analog CH1 Mic Gain Volume", ADCX140_CH1_CFG1, 2, 42, 0,
599 	SOC_SINGLE_TLV("Analog CH2 Mic Gain Volume", ADCX140_CH2_CFG1, 2, 42, 0,
601 	SOC_SINGLE_TLV("Analog CH3 Mic Gain Volume", ADCX140_CH3_CFG1, 2, 42, 0,
603 	SOC_SINGLE_TLV("Analog CH4 Mic Gain Volume", ADCX140_CH4_CFG1, 2, 42, 0,
606 	SOC_SINGLE_TLV("DRE Threshold", ADCX140_DRE_CFG0, 4, 9, 0,
608 	SOC_SINGLE_TLV("DRE Max Gain", ADCX140_DRE_CFG0, 0, 12, 0,
611 	SOC_SINGLE_TLV("AGC Threshold", ADCX140_AGC_CFG0, 4, 15, 0,
613 	SOC_SINGLE_TLV("AGC Max Gain", ADCX140_AGC_CFG0, 0, 13, 0,
617 			0, 0xff, 0, dig_vol_tlv),
619 			0, 0xff, 0, dig_vol_tlv),
621 			0, 0xff, 0, dig_vol_tlv),
623 			0, 0xff, 0, dig_vol_tlv),
625 			0, 0xff, 0, dig_vol_tlv),
627 			0, 0xff, 0, dig_vol_tlv),
629 			0, 0xff, 0, dig_vol_tlv),
631 			0, 0xff, 0, dig_vol_tlv),
636 	int ret = 0;  in adcx140_reset()
639 		gpiod_direction_output(adcx140->gpio_reset, 0);  in adcx140_reset()
656 	int pwr_ctrl = 0;  in adcx140_pwr_ctrl()
674 	u8 data = 0;  in adcx140_hw_params()
702 	return 0;  in adcx140_hw_params()
710 	u8 iface_reg1 = 0;  in adcx140_set_dai_fmt()
711 	u8 iface_reg2 = 0;  in adcx140_set_dai_fmt()
712 	int offset = 0;  in adcx140_set_dai_fmt()
786 	return 0;  in adcx140_set_dai_fmt()
818 	return 0;  in adcx140_set_dai_tdm_slot()
830 	u32 gpo_output_val = 0;  in adcx140_configure_gpo()
834 	for (i = 0; i < ADCX140_NUM_GPOS; i++) {  in adcx140_configure_gpo()
842 		if (gpo_outputs[0] > ADCX140_GPO_CFG_MAX) {  in adcx140_configure_gpo()
852 		gpo_output_val = gpo_outputs[0] << ADCX140_GPO_SHIFT |  in adcx140_configure_gpo()
860 	return 0;  in adcx140_configure_gpo()
866 	int gpio_count = 0;  in adcx140_configure_gpio()
868 	u32 gpio_output_val = 0;  in adcx140_configure_gpio()
873 	if (gpio_count == 0)  in adcx140_configure_gpio()
874 		return 0;  in adcx140_configure_gpio()
884 	if (gpio_outputs[0] > ADCX140_GPIO_CFG_MAX) {  in adcx140_configure_gpio()
894 	gpio_output_val = gpio_outputs[0] << ADCX140_GPIO_SHIFT  in adcx140_configure_gpio()
909 	u32 pdm_edge_val = 0;  in adcx140_codec_probe()
912 	u32 gpi_input_val = 0;  in adcx140_codec_probe()
956 	if (pdm_count <= ADCX140_NUM_PDM_EDGES && pdm_count > 0) {  in adcx140_codec_probe()
963 		for (i = 0; i < pdm_count; i++)  in adcx140_codec_probe()
973 	if (gpi_count <= ADCX140_NUM_GPI_PINS && gpi_count > 0) {  in adcx140_codec_probe()
1042 	return 0;  in adcx140_set_bias_level()
1055 	.idle_bias_on		= 0,
1134 	{ "tlv320adc3140", 0 },