1 // SPDX-License-Identifier: GPL-2.0
3  * rt715.c -- rt715 ALSA SoC audio driver
32 #include <sound/soc-dapm.h>
61 	ret = regmap_read(rt715->regmap, addr_l, r_val);  in rt715_get_gain()
68 	ret = regmap_read(rt715->regmap, addr_h, l_val);  in rt715_get_gain()
73 /* For Verb-Set Amplifier Gain (Verb ID = 3h) */
81 		(struct soc_mixer_control *)kcontrol->private_value;  in rt715_set_amp_gain_put()
88 		if (ucontrol->value.integer.value[i] != rt715->kctl_2ch_vol_ori[i]) {  in rt715_set_amp_gain_put()
95 	addr_h = mc->reg;  in rt715_set_amp_gain_put()
96 	addr_l = mc->rreg;  in rt715_set_amp_gain_put()
98 	if (mc->shift == RT715_DIR_OUT_SFT) /* output */  in rt715_set_amp_gain_put()
105 	if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)  in rt715_set_amp_gain_put()
106 		regmap_write(rt715->regmap,  in rt715_set_amp_gain_put()
110 	rt715->kctl_2ch_vol_ori[0] = ucontrol->value.integer.value[0];  in rt715_set_amp_gain_put()
112 	val_ll = ((ucontrol->value.integer.value[0]) & 0x7f);  in rt715_set_amp_gain_put()
113 	if (val_ll > mc->max)  in rt715_set_amp_gain_put()
114 		val_ll = mc->max;  in rt715_set_amp_gain_put()
119 	rt715->kctl_2ch_vol_ori[1] = ucontrol->value.integer.value[1];  in rt715_set_amp_gain_put()
121 	val_lr = ((ucontrol->value.integer.value[1]) & 0x7f);  in rt715_set_amp_gain_put()
122 	if (val_lr > mc->max)  in rt715_set_amp_gain_put()
123 		val_lr = mc->max;  in rt715_set_amp_gain_put()
131 			val_h = (1 << mc->shift) | (3 << 4);  in rt715_set_amp_gain_put()
132 			regmap_write(rt715->regmap, addr_h,  in rt715_set_amp_gain_put()
134 			regmap_write(rt715->regmap, addr_l,  in rt715_set_amp_gain_put()
138 			val_h = (1 << mc->shift) | (1 << 5);  in rt715_set_amp_gain_put()
139 			regmap_write(rt715->regmap, addr_h,  in rt715_set_amp_gain_put()
142 			val_h = (1 << mc->shift) | (1 << 4);  in rt715_set_amp_gain_put()
143 			regmap_write(rt715->regmap, addr_l,  in rt715_set_amp_gain_put()
147 		if (mc->shift == RT715_DIR_OUT_SFT) /* output */  in rt715_set_amp_gain_put()
159 	if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)  in rt715_set_amp_gain_put()
160 		regmap_write(rt715->regmap,  in rt715_set_amp_gain_put()
171 		(struct soc_mixer_control *)kcontrol->private_value;  in rt715_set_amp_gain_get()
175 	addr_h = mc->reg;  in rt715_set_amp_gain_get()
176 	addr_l = mc->rreg;  in rt715_set_amp_gain_get()
177 	if (mc->shift == RT715_DIR_OUT_SFT) /* output */  in rt715_set_amp_gain_get()
184 	if (mc->invert) {  in rt715_set_amp_gain_get()
193 	ucontrol->value.integer.value[0] = read_ll;  in rt715_set_amp_gain_get()
194 	ucontrol->value.integer.value[1] = read_rl;  in rt715_set_amp_gain_get()
217 		if (ucontrol->value.integer.value[i] != rt715->kctl_8ch_switch_ori[i])  in rt715_set_main_switch_put()
227 		if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)  in rt715_set_main_switch_put()
228 			regmap_write(rt715->regmap,  in rt715_set_main_switch_put()
233 		rt715->kctl_8ch_switch_ori[j * 2] =  in rt715_set_main_switch_put()
234 			ucontrol->value.integer.value[j * 2];  in rt715_set_main_switch_put()
235 		val_ll = (!ucontrol->value.integer.value[j * 2]) << 7;  in rt715_set_main_switch_put()
241 		rt715->kctl_8ch_switch_ori[j * 2 + 1] =  in rt715_set_main_switch_put()
242 			ucontrol->value.integer.value[j * 2 + 1];  in rt715_set_main_switch_put()
243 		val_lr = (!ucontrol->value.integer.value[j * 2 + 1]) << 7;  in rt715_set_main_switch_put()
252 				regmap_write(rt715->regmap, addr_h,  in rt715_set_main_switch_put()
254 				regmap_write(rt715->regmap, addr_l,  in rt715_set_main_switch_put()
259 				regmap_write(rt715->regmap, addr_h,  in rt715_set_main_switch_put()
263 				regmap_write(rt715->regmap, addr_l,  in rt715_set_main_switch_put()
275 	if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)  in rt715_set_main_switch_put()
276 		regmap_write(rt715->regmap,  in rt715_set_main_switch_put()
300 		ucontrol->value.integer.value[i * 2] = !(read_ll & 0x80);  in rt715_set_main_switch_get()
301 		ucontrol->value.integer.value[i * 2 + 1] = !(read_rl & 0x80);  in rt715_set_main_switch_get()
325 		if (ucontrol->value.integer.value[i] != rt715->kctl_8ch_vol_ori[i])  in rt715_set_main_vol_put()
334 		if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)  in rt715_set_main_vol_put()
335 			regmap_write(rt715->regmap,  in rt715_set_main_vol_put()
340 		rt715->kctl_8ch_vol_ori[j * 2] = ucontrol->value.integer.value[j * 2];  in rt715_set_main_vol_put()
341 		val_ll = ((ucontrol->value.integer.value[j * 2]) & 0x7f);  in rt715_set_main_vol_put()
349 		rt715->kctl_8ch_vol_ori[j * 2 + 1] =  in rt715_set_main_vol_put()
350 			ucontrol->value.integer.value[j * 2 + 1];  in rt715_set_main_vol_put()
351 		val_lr = ((ucontrol->value.integer.value[j * 2 + 1]) & 0x7f);  in rt715_set_main_vol_put()
361 				regmap_write(rt715->regmap, addr_h,  in rt715_set_main_vol_put()
363 				regmap_write(rt715->regmap, addr_l,  in rt715_set_main_vol_put()
368 				regmap_write(rt715->regmap, addr_h,  in rt715_set_main_vol_put()
372 				regmap_write(rt715->regmap, addr_l,  in rt715_set_main_vol_put()
384 	if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)  in rt715_set_main_vol_put()
385 		regmap_write(rt715->regmap,  in rt715_set_main_vol_put()
409 		ucontrol->value.integer.value[i * 2] = read_ll & 0x7f;  in rt715_set_main_vol_get()
410 		ucontrol->value.integer.value[i * 2 + 1] = read_rl & 0x7f;  in rt715_set_main_vol_get()
416 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0);
422 	uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;  in rt715_switch_info()
423 	uinfo->count = 8;  in rt715_switch_info()
424 	uinfo->value.integer.min = 0;  in rt715_switch_info()
425 	uinfo->value.integer.max = 1;  in rt715_switch_info()
432 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;  in rt715_vol_info()
433 	uinfo->count = 8;  in rt715_vol_info()
434 	uinfo->value.integer.min = 0;  in rt715_vol_info()
435 	uinfo->value.integer.max = 0x3f;  in rt715_vol_info()
510 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;  in rt715_mux_get()
514 	/* nid = e->reg, vid = 0xf01 */  in rt715_mux_get()
515 	reg = RT715_VERB_SET_CONNECT_SEL | e->reg;  in rt715_mux_get()
516 	ret = regmap_read(rt715->regmap, reg, &val);  in rt715_mux_get()
518 		dev_err(component->dev, "%s: sdw read failed: %d\n",  in rt715_mux_get()
524 	 * The first two indices of ADC Mux 24/25 are routed to the same  in rt715_mux_get()
525 	 * hardware source. ie, ADC Mux 24 0/1 will both connect to MIC2.  in rt715_mux_get()
528 	if ((e->reg == RT715_MUX_IN3 || e->reg == RT715_MUX_IN4) && (val > 0))  in rt715_mux_get()
529 		val -= 1;  in rt715_mux_get()
530 	ucontrol->value.enumerated.item[0] = val;  in rt715_mux_get()
543 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;  in rt715_mux_put()
544 	unsigned int *item = ucontrol->value.enumerated.item;  in rt715_mux_put()
548 	if (item[0] >= e->items)  in rt715_mux_put()
549 		return -EINVAL;  in rt715_mux_put()
551 	/* Verb ID = 0x701h, nid = e->reg */  in rt715_mux_put()
552 	val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;  in rt715_mux_put()
554 	reg = RT715_VERB_SET_CONNECT_SEL | e->reg;  in rt715_mux_put()
555 	ret = regmap_read(rt715->regmap, reg, &val2);  in rt715_mux_put()
557 		dev_err(component->dev, "%s: sdw read failed: %d\n",  in rt715_mux_put()
568 		reg = RT715_VERB_SET_CONNECT_SEL | e->reg;  in rt715_mux_put()
569 		regmap_write(rt715->regmap, reg, val);  in rt715_mux_put()
590  * Due to mux design for nid 24 (MUX_IN3)/25 (MUX_IN4), connection index 0 and
633 	SOC_DAPM_ENUM_EXT("ADC 22 Mux", rt715_adc22_enum,
637 	SOC_DAPM_ENUM_EXT("ADC 23 Mux", rt715_adc23_enum,
641 	SOC_DAPM_ENUM_EXT("ADC 24 Mux", rt715_adc24_enum,
645 	SOC_DAPM_ENUM_EXT("ADC 25 Mux", rt715_adc25_enum,
657 	SND_SOC_DAPM_ADC("ADC 07", NULL, RT715_SET_STREAMID_MIC_ADC, 4, 0),
658 	SND_SOC_DAPM_ADC("ADC 08", NULL, RT715_SET_STREAMID_LINE_ADC, 4, 0),
659 	SND_SOC_DAPM_ADC("ADC 09", NULL, RT715_SET_STREAMID_MIX_ADC, 4, 0),
660 	SND_SOC_DAPM_ADC("ADC 27", NULL, RT715_SET_STREAMID_MIX_ADC2, 4, 0),
661 	SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0,
663 	SND_SOC_DAPM_MUX("ADC 23 Mux", SND_SOC_NOPM, 0, 0,
665 	SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0,
667 	SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0,
674 	{"DP6TX", NULL, "ADC 09"},
675 	{"DP6TX", NULL, "ADC 08"},
676 	{"DP4TX", NULL, "ADC 07"},
677 	{"DP4TX", NULL, "ADC 27"},
678 	{"ADC 09", NULL, "ADC 22 Mux"},
679 	{"ADC 08", NULL, "ADC 23 Mux"},
680 	{"ADC 07", NULL, "ADC 24 Mux"},
681 	{"ADC 27", NULL, "ADC 25 Mux"},
682 	{"ADC 22 Mux", "MIC1", "MIC1"},
683 	{"ADC 22 Mux", "MIC2", "MIC2"},
684 	{"ADC 22 Mux", "LINE1", "LINE1"},
685 	{"ADC 22 Mux", "LINE2", "LINE2"},
686 	{"ADC 22 Mux", "DMIC1", "DMIC1"},
687 	{"ADC 22 Mux", "DMIC2", "DMIC2"},
688 	{"ADC 22 Mux", "DMIC3", "DMIC3"},
689 	{"ADC 22 Mux", "DMIC4", "DMIC4"},
690 	{"ADC 23 Mux", "MIC1", "MIC1"},
691 	{"ADC 23 Mux", "MIC2", "MIC2"},
692 	{"ADC 23 Mux", "LINE1", "LINE1"},
693 	{"ADC 23 Mux", "LINE2", "LINE2"},
694 	{"ADC 23 Mux", "DMIC1", "DMIC1"},
695 	{"ADC 23 Mux", "DMIC2", "DMIC2"},
696 	{"ADC 23 Mux", "DMIC3", "DMIC3"},
697 	{"ADC 23 Mux", "DMIC4", "DMIC4"},
698 	{"ADC 24 Mux", "MIC2", "MIC2"},
699 	{"ADC 24 Mux", "DMIC1", "DMIC1"},
700 	{"ADC 24 Mux", "DMIC2", "DMIC2"},
701 	{"ADC 24 Mux", "DMIC3", "DMIC3"},
702 	{"ADC 24 Mux", "DMIC4", "DMIC4"},
703 	{"ADC 25 Mux", "MIC1", "MIC1"},
704 	{"ADC 25 Mux", "DMIC1", "DMIC1"},
705 	{"ADC 25 Mux", "DMIC2", "DMIC2"},
706 	{"ADC 25 Mux", "DMIC3", "DMIC3"},
707 	{"ADC 25 Mux", "DMIC4", "DMIC4"},
719 		if (dapm->bias_level == SND_SOC_BIAS_STANDBY) {  in rt715_set_bias_level()
720 			regmap_write(rt715->regmap,  in rt715_set_bias_level()
728 		regmap_write(rt715->regmap,  in rt715_set_bias_level()
736 	dapm->bias_level = level;  in rt715_set_bias_level()
761 		return -ENOMEM;  in rt715_set_sdw_stream()
763 	stream->sdw_stream = sdw_stream;  in rt715_set_sdw_stream()
767 		dai->playback_dma_data = stream;  in rt715_set_sdw_stream()
769 		dai->capture_dma_data = stream;  in rt715_set_sdw_stream()
789 	struct snd_soc_component *component = dai->component;  in rt715_pcm_hw_params()
801 		return -EINVAL;  in rt715_pcm_hw_params()
803 	if (!rt715->slave)  in rt715_pcm_hw_params()
804 		return -EINVAL;  in rt715_pcm_hw_params()
806 	switch (dai->id) {  in rt715_pcm_hw_params()
810 		rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa500);  in rt715_pcm_hw_params()
815 		rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa000);  in rt715_pcm_hw_params()
818 		dev_err(component->dev, "Invalid DAI id %d\n", dai->id);  in rt715_pcm_hw_params()
819 		return -EINVAL;  in rt715_pcm_hw_params()
828 	port_config.ch_mask = (1 << (num_channels)) - 1;  in rt715_pcm_hw_params()
831 	retval = sdw_stream_add_slave(rt715->slave, &stream_config,  in rt715_pcm_hw_params()
832 					&port_config, 1, stream->sdw_stream);  in rt715_pcm_hw_params()
834 		dev_err(dai->dev, "Unable to configure port\n");  in rt715_pcm_hw_params()
840 	/* bit 15 Stream Type 0:PCM 1:Non-PCM, should always be PCM */  in rt715_pcm_hw_params()
848 		dev_err(component->dev, "Unsupported sample rate %d\n",  in rt715_pcm_hw_params()
850 		return -EINVAL;  in rt715_pcm_hw_params()
855 		val |= (params_channels(params) - 1);  in rt715_pcm_hw_params()
857 		dev_err(component->dev, "Unsupported channels %d\n",  in rt715_pcm_hw_params()
859 		return -EINVAL;  in rt715_pcm_hw_params()
879 		return -EINVAL;  in rt715_pcm_hw_params()
882 	regmap_write(rt715->regmap, RT715_MIC_ADC_FORMAT_H, val);  in rt715_pcm_hw_params()
883 	regmap_write(rt715->regmap, RT715_MIC_LINE_FORMAT_H, val);  in rt715_pcm_hw_params()
884 	regmap_write(rt715->regmap, RT715_MIX_ADC_FORMAT_H, val);  in rt715_pcm_hw_params()
885 	regmap_write(rt715->regmap, RT715_MIX_ADC2_FORMAT_H, val);  in rt715_pcm_hw_params()
893 	struct snd_soc_component *component = dai->component;  in rt715_pcm_hw_free()
898 	if (!rt715->slave)  in rt715_pcm_hw_free()
899 		return -EINVAL;  in rt715_pcm_hw_free()
901 	sdw_stream_remove_slave(rt715->slave, stream->sdw_stream);  in rt715_pcm_hw_free()
918 		.name = "rt715-aif1",
930 		.name = "rt715-aif2",
956 	clk_freq = (rt715->params.curr_dr_freq >> 1);  in rt715_clock_config()
978 		return -EINVAL;  in rt715_clock_config()
981 	regmap_write(rt715->regmap, 0xe0, value);  in rt715_clock_config()
982 	regmap_write(rt715->regmap, 0xf0, value);  in rt715_clock_config()
995 		return -ENOMEM;  in rt715_init()
998 	rt715->slave = slave;  in rt715_init()
999 	rt715->regmap = regmap;  in rt715_init()
1000 	rt715->sdw_regmap = sdw_regmap;  in rt715_init()
1006 	rt715->hw_init = false;  in rt715_init()
1007 	rt715->first_hw_init = false;  in rt715_init()
1021 	if (rt715->hw_init)  in rt715_io_init()
1027 	if (!rt715->first_hw_init) {  in rt715_io_init()
1029 		pm_runtime_set_autosuspend_delay(&slave->dev, 3000);  in rt715_io_init()
1030 		pm_runtime_use_autosuspend(&slave->dev);  in rt715_io_init()
1033 		pm_runtime_set_active(&slave->dev);  in rt715_io_init()
1036 		pm_runtime_mark_last_busy(&slave->dev);  in rt715_io_init()
1038 		pm_runtime_enable(&slave->dev);  in rt715_io_init()
1041 	pm_runtime_get_noresume(&slave->dev);  in rt715_io_init()
1044 	regmap_write(rt715->regmap, RT715_SET_GAIN_LINE_ADC_H, 0xb080);  in rt715_io_init()
1045 	regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC_H, 0xb080);  in rt715_io_init()
1047 	regmap_write(rt715->regmap, RT715_SET_GAIN_MIC_ADC_H, 0xb080);  in rt715_io_init()
1048 	regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC2_H, 0xb080);  in rt715_io_init()
1051 	regmap_write(rt715->regmap, RT715_SET_PIN_DMIC1, 0x20);  in rt715_io_init()
1052 	regmap_write(rt715->regmap, RT715_SET_PIN_DMIC2, 0x20);  in rt715_io_init()
1053 	regmap_write(rt715->regmap, RT715_SET_PIN_DMIC3, 0x20);  in rt715_io_init()
1054 	regmap_write(rt715->regmap, RT715_SET_PIN_DMIC4, 0x20);  in rt715_io_init()
1056 	regmap_write(rt715->regmap, RT715_SET_STREAMID_LINE_ADC, 0x10);  in rt715_io_init()
1057 	regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC, 0x10);  in rt715_io_init()
1058 	regmap_write(rt715->regmap, RT715_SET_STREAMID_MIC_ADC, 0x10);  in rt715_io_init()
1059 	regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC2, 0x10);  in rt715_io_init()
1061 	regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT1, 0xd0);  in rt715_io_init()
1062 	regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT2, 0x11);  in rt715_io_init()
1063 	regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT3, 0xa1);  in rt715_io_init()
1064 	regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT4, 0x81);  in rt715_io_init()
1065 	regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT1, 0xd1);  in rt715_io_init()
1066 	regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT2, 0x11);  in rt715_io_init()
1067 	regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT3, 0xa1);  in rt715_io_init()
1068 	regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT4, 0x81);  in rt715_io_init()
1069 	regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT1, 0xd0);  in rt715_io_init()
1070 	regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT2, 0x11);  in rt715_io_init()
1071 	regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT3, 0xa1);  in rt715_io_init()
1072 	regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT4, 0x81);  in rt715_io_init()
1073 	regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT1, 0xd1);  in rt715_io_init()
1074 	regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT2, 0x11);  in rt715_io_init()
1075 	regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT3, 0xa1);  in rt715_io_init()
1076 	regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT4, 0x81);  in rt715_io_init()
1079 	regmap_write(rt715->regmap, RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);  in rt715_io_init()
1081 	if (rt715->first_hw_init)  in rt715_io_init()
1082 		regcache_mark_dirty(rt715->regmap);  in rt715_io_init()
1084 		rt715->first_hw_init = true;  in rt715_io_init()
1087 	rt715->hw_init = true;  in rt715_io_init()
1089 	pm_runtime_mark_last_busy(&slave->dev);  in rt715_io_init()
1090 	pm_runtime_put_autosuspend(&slave->dev);  in rt715_io_init()