Lines Matching +full:adc +full:- +full:mux
1 // SPDX-License-Identifier: GPL-2.0-only
3 // rt5682.c -- RT5682 ALSA SoC audio component driver
26 #include <sound/soc-dapm.h>
55 ret = regmap_multi_reg_write(rt5682->regmap, patch_list, in rt5682_apply_patch_list()
744 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
745 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
780 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
783 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
786 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
789 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
792 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
802 SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum);
808 SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum);
812 regmap_write(rt5682->regmap, RT5682_RESET, 0); in rt5682_reset()
813 if (!rt5682->is_sdw) in rt5682_reset()
814 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1); in rt5682_reset()
819 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
842 return -EINVAL; in rt5682_sel_asrc_clk_src()
868 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type); in rt5682_button_detect()
889 if (rt5682->is_sdw) in rt5682_enable_push_button_irq()
913 * rt5682_headset_detect - Detect headset.
924 struct snd_soc_dapm_context *dapm = &component->dapm; in rt5682_headset_detect()
957 rt5682->jack_type = SND_JACK_HEADSET; in rt5682_headset_detect()
963 rt5682->jack_type = SND_JACK_HEADPHONE; in rt5682_headset_detect()
996 rt5682->jack_type = 0; in rt5682_headset_detect()
999 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type); in rt5682_headset_detect()
1000 return rt5682->jack_type; in rt5682_headset_detect()
1009 rt5682->hs_jack = hs_jack; in rt5682_set_jack_detect()
1012 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, in rt5682_set_jack_detect()
1014 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, in rt5682_set_jack_detect()
1016 cancel_delayed_work_sync(&rt5682->jack_detect_work); in rt5682_set_jack_detect()
1021 if (!rt5682->is_sdw) { in rt5682_set_jack_detect()
1022 switch (rt5682->pdata.jd_src) { in rt5682_set_jack_detect()
1037 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, in rt5682_set_jack_detect()
1039 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, in rt5682_set_jack_detect()
1043 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2, in rt5682_set_jack_detect()
1045 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, in rt5682_set_jack_detect()
1048 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4, in rt5682_set_jack_detect()
1049 0x7f7f, (rt5682->pdata.btndet_delay << 8 | in rt5682_set_jack_detect()
1050 rt5682->pdata.btndet_delay)); in rt5682_set_jack_detect()
1051 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5, in rt5682_set_jack_detect()
1052 0x7f7f, (rt5682->pdata.btndet_delay << 8 | in rt5682_set_jack_detect()
1053 rt5682->pdata.btndet_delay)); in rt5682_set_jack_detect()
1054 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6, in rt5682_set_jack_detect()
1055 0x7f7f, (rt5682->pdata.btndet_delay << 8 | in rt5682_set_jack_detect()
1056 rt5682->pdata.btndet_delay)); in rt5682_set_jack_detect()
1057 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7, in rt5682_set_jack_detect()
1058 0x7f7f, (rt5682->pdata.btndet_delay << 8 | in rt5682_set_jack_detect()
1059 rt5682->pdata.btndet_delay)); in rt5682_set_jack_detect()
1061 &rt5682->jack_detect_work, in rt5682_set_jack_detect()
1066 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, in rt5682_set_jack_detect()
1068 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, in rt5682_set_jack_detect()
1073 dev_warn(component->dev, "Wrong JD source\n"); in rt5682_set_jack_detect()
1087 while (!rt5682->component) in rt5682_jack_detect_handler()
1090 while (!rt5682->component->card->instantiated) in rt5682_jack_detect_handler()
1093 mutex_lock(&rt5682->calibrate_mutex); in rt5682_jack_detect_handler()
1095 val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL) in rt5682_jack_detect_handler()
1099 if (rt5682->jack_type == 0) { in rt5682_jack_detect_handler()
1101 rt5682->jack_type = in rt5682_jack_detect_handler()
1102 rt5682_headset_detect(rt5682->component, 1); in rt5682_jack_detect_handler()
1103 rt5682->irq_work_delay_time = 0; in rt5682_jack_detect_handler()
1104 } else if ((rt5682->jack_type & SND_JACK_HEADSET) == in rt5682_jack_detect_handler()
1107 rt5682->jack_type = SND_JACK_HEADSET; in rt5682_jack_detect_handler()
1108 btn_type = rt5682_button_detect(rt5682->component); in rt5682_jack_detect_handler()
1120 rt5682->jack_type |= SND_JACK_BTN_0; in rt5682_jack_detect_handler()
1125 rt5682->jack_type |= SND_JACK_BTN_1; in rt5682_jack_detect_handler()
1130 rt5682->jack_type |= SND_JACK_BTN_2; in rt5682_jack_detect_handler()
1135 rt5682->jack_type |= SND_JACK_BTN_3; in rt5682_jack_detect_handler()
1140 dev_err(rt5682->component->dev, in rt5682_jack_detect_handler()
1148 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); in rt5682_jack_detect_handler()
1149 rt5682->irq_work_delay_time = 50; in rt5682_jack_detect_handler()
1152 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, in rt5682_jack_detect_handler()
1157 if (!rt5682->is_sdw) { in rt5682_jack_detect_handler()
1158 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | in rt5682_jack_detect_handler()
1160 schedule_delayed_work(&rt5682->jd_check_work, 0); in rt5682_jack_detect_handler()
1162 cancel_delayed_work_sync(&rt5682->jd_check_work); in rt5682_jack_detect_handler()
1165 mutex_unlock(&rt5682->calibrate_mutex); in rt5682_jack_detect_handler()
1178 /* ADC Digital Volume Control */
1179 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1181 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1184 /* ADC Boost Volume Control */
1185 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1195 if (rt5682->sysclk < target) { in rt5682_div_sel()
1196 dev_err(rt5682->component->dev, in rt5682_div_sel()
1197 "sysclk rate %d is too low\n", rt5682->sysclk); in rt5682_div_sel()
1201 for (i = 0; i < size - 1; i++) { in rt5682_div_sel()
1202 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]); in rt5682_div_sel()
1203 if (target * div[i] == rt5682->sysclk) in rt5682_div_sel()
1205 if (target * div[i + 1] > rt5682->sysclk) { in rt5682_div_sel()
1206 dev_dbg(rt5682->component->dev, in rt5682_div_sel()
1208 rt5682->sysclk); in rt5682_div_sel()
1213 if (target * div[i] < rt5682->sysclk) in rt5682_div_sel()
1214 dev_err(rt5682->component->dev, in rt5682_div_sel()
1215 "sysclk rate %d is too high\n", rt5682->sysclk); in rt5682_div_sel()
1217 return size - 1; in rt5682_div_sel()
1221 * set_dmic_clk - Set parameter of dmic.
1234 snd_soc_dapm_to_component(w->dapm); in set_dmic_clk()
1239 if (rt5682->pdata.dmic_clk_rate) in set_dmic_clk()
1240 dmic_clk_rate = rt5682->pdata.dmic_clk_rate; in set_dmic_clk()
1254 snd_soc_dapm_to_component(w->dapm); in set_filter_clk()
1260 if (rt5682->is_sdw) in set_filter_clk()
1265 if (w->shift == RT5682_PWR_ADC_S1F_BIT && in set_filter_clk()
1267 ref = 256 * rt5682->lrck[RT5682_AIF2]; in set_filter_clk()
1269 ref = 256 * rt5682->lrck[RT5682_AIF1]; in set_filter_clk()
1273 if (w->shift == RT5682_PWR_ADC_S1F_BIT) in set_filter_clk()
1283 if (rt5682->sysclk <= 12288000 * div_o[idx]) in set_filter_clk()
1299 snd_soc_dapm_to_component(w->dapm); in is_sys_clk_from_pll1()
1314 snd_soc_dapm_to_component(w->dapm); in is_sys_clk_from_pll2()
1329 snd_soc_dapm_to_component(w->dapm); in is_using_asrc()
1331 switch (w->shift) { in is_using_asrc()
1370 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1377 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1404 /* MX-26 [13] [5] */
1406 "DAC MIX", "ADC"
1423 /* STO1 ADC Source */
1424 /* MX-26 [11:10] [3:2] */
1444 /* MX-26 [12] [4] */
1463 /* MX-79 [6:4] I2S1 ADC data location */
1480 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1483 /* MX-2B [4], MX-2B [0]*/
1514 snd_soc_dapm_to_component(w->dapm); in rt5682_hp_event()
1545 snd_soc_dapm_to_component(w->dapm); in set_dmic_power()
1549 if (rt5682->pdata.dmic_delay) in set_dmic_power()
1550 delay = rt5682->pdata.dmic_delay; in set_dmic_power()
1567 if (!rt5682->jack_type) { in set_dmic_power()
1568 if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS")) in set_dmic_power()
1571 if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2")) in set_dmic_power()
1585 snd_soc_dapm_to_component(w->dapm); in rt5682_set_verf()
1589 switch (w->shift) { in rt5682_set_verf()
1604 switch (w->shift) { in rt5682_set_verf()
1657 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1705 /* ADC Mux */
1706 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1708 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1710 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1712 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1714 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1716 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1718 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1721 /* ADC Mixer */
1722 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1725 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1728 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1732 /* ADC PGA */
1733 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1747 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1749 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1751 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1753 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1755 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1758 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1761 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0,
1763 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0,
1782 /* DAC channel Mux */
1840 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1841 {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1842 {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1848 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1850 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1851 {"ADC STO1 ASRC", NULL, "DA ASRC"},
1852 {"ADC STO1 ASRC", NULL, "CLKDET"},
1878 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1879 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1880 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1881 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1883 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1884 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1885 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1886 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1888 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1889 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1890 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1891 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1893 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1894 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1895 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1897 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1898 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1899 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1901 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1902 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1904 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1905 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1906 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1907 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1908 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1909 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1910 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1911 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1912 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1913 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1914 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1915 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1916 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1917 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1918 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1919 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1921 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1922 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1923 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1924 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1925 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1927 {"AIF1TX", NULL, "ADCDAT Mux"},
1928 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1929 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1930 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1931 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1932 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1933 {"AIF2TX", NULL, "ADCDAT Mux"},
1937 {"SDWTX", NULL, "ADCDAT Mux"},
1955 {"DAC L Mux", "IF1", "IF1 DAC1 L"},
1956 {"DAC L Mux", "SOUND", "SOUND DAC L"},
1957 {"DAC R Mux", "IF1", "IF1 DAC1 R"},
1958 {"DAC R Mux", "SOUND", "SOUND DAC R"},
1960 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1961 {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"},
1962 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1963 {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"},
1999 struct snd_soc_component *component = dai->component; in rt5682_set_tdm_slot()
2025 return -EINVAL; in rt5682_set_tdm_slot()
2034 return -EINVAL; in rt5682_set_tdm_slot()
2054 return -EINVAL; in rt5682_set_tdm_slot()
2068 struct snd_soc_component *component = dai->component; in rt5682_hw_params()
2073 rt5682->lrck[dai->id] = params_rate(params); in rt5682_hw_params()
2074 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]); in rt5682_hw_params()
2078 dev_err(component->dev, "Unsupported frame size: %d\n", in rt5682_hw_params()
2080 return -EINVAL; in rt5682_hw_params()
2083 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", in rt5682_hw_params()
2084 rt5682->lrck[dai->id], pre_div, dai->id); in rt5682_hw_params()
2106 return -EINVAL; in rt5682_hw_params()
2109 switch (dai->id) { in rt5682_hw_params()
2113 if (rt5682->master[RT5682_AIF1]) { in rt5682_hw_params()
2118 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); in rt5682_hw_params()
2132 if (rt5682->master[RT5682_AIF2]) { in rt5682_hw_params()
2147 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); in rt5682_hw_params()
2148 return -EINVAL; in rt5682_hw_params()
2156 struct snd_soc_component *component = dai->component; in rt5682_set_dai_fmt()
2162 rt5682->master[dai->id] = 1; in rt5682_set_dai_fmt()
2165 rt5682->master[dai->id] = 0; in rt5682_set_dai_fmt()
2168 return -EINVAL; in rt5682_set_dai_fmt()
2179 if (dai->id == RT5682_AIF1) in rt5682_set_dai_fmt()
2182 return -EINVAL; in rt5682_set_dai_fmt()
2185 if (dai->id == RT5682_AIF1) in rt5682_set_dai_fmt()
2189 return -EINVAL; in rt5682_set_dai_fmt()
2192 return -EINVAL; in rt5682_set_dai_fmt()
2211 return -EINVAL; in rt5682_set_dai_fmt()
2214 switch (dai->id) { in rt5682_set_dai_fmt()
2222 tdm_ctrl | rt5682->master[dai->id]); in rt5682_set_dai_fmt()
2225 if (rt5682->master[dai->id] == 0) in rt5682_set_dai_fmt()
2232 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); in rt5682_set_dai_fmt()
2233 return -EINVAL; in rt5682_set_dai_fmt()
2244 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src) in rt5682_set_component_sysclk()
2265 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); in rt5682_set_component_sysclk()
2266 return -EINVAL; in rt5682_set_component_sysclk()
2271 if (rt5682->master[RT5682_AIF2]) { in rt5682_set_component_sysclk()
2277 rt5682->sysclk = freq; in rt5682_set_component_sysclk()
2278 rt5682->sysclk_src = clk_id; in rt5682_set_component_sysclk()
2280 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", in rt5682_set_component_sysclk()
2295 if (source == rt5682->pll_src[pll_id] && in rt5682_set_component_pll()
2296 freq_in == rt5682->pll_in[pll_id] && in rt5682_set_component_pll()
2297 freq_out == rt5682->pll_out[pll_id]) in rt5682_set_component_pll()
2301 dev_dbg(component->dev, "PLL disabled\n"); in rt5682_set_component_pll()
2303 rt5682->pll_in[pll_id] = 0; in rt5682_set_component_pll()
2304 rt5682->pll_out[pll_id] = 0; in rt5682_set_component_pll()
2318 dev_err(component->dev, "Unknown PLL2 Source %d\n", in rt5682_set_component_pll()
2320 return -EINVAL; in rt5682_set_component_pll()
2330 dev_err(component->dev, "Unsupport input clock %d\n", in rt5682_set_component_pll()
2334 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", in rt5682_set_component_pll()
2342 dev_err(component->dev, "Unsupport input clock %d\n", in rt5682_set_component_pll()
2346 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", in rt5682_set_component_pll()
2386 dev_err(component->dev, "Unknown PLL1 Source %d\n", in rt5682_set_component_pll()
2388 return -EINVAL; in rt5682_set_component_pll()
2393 dev_err(component->dev, "Unsupport input clock %d\n", in rt5682_set_component_pll()
2398 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", in rt5682_set_component_pll()
2409 rt5682->pll_in[pll_id] = freq_in; in rt5682_set_component_pll()
2410 rt5682->pll_out[pll_id] = freq_out; in rt5682_set_component_pll()
2411 rt5682->pll_src[pll_id] = source; in rt5682_set_component_pll()
2418 struct snd_soc_component *component = dai->component; in rt5682_set_bclk1_ratio()
2421 rt5682->bclk[dai->id] = ratio; in rt5682_set_bclk1_ratio()
2441 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio); in rt5682_set_bclk1_ratio()
2442 return -EINVAL; in rt5682_set_bclk1_ratio()
2450 struct snd_soc_component *component = dai->component; in rt5682_set_bclk2_ratio()
2453 rt5682->bclk[dai->id] = ratio; in rt5682_set_bclk2_ratio()
2467 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio); in rt5682_set_bclk2_ratio()
2468 return -EINVAL; in rt5682_set_bclk2_ratio()
2481 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, in rt5682_set_bias_level()
2483 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, in rt5682_set_bias_level()
2489 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, in rt5682_set_bias_level()
2493 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, in rt5682_set_bias_level()
2495 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, in rt5682_set_bias_level()
2512 if (!rt5682->master[RT5682_AIF1]) { in rt5682_clk_check()
2513 dev_dbg(rt5682->component->dev, "sysclk/dai not set correctly\n"); in rt5682_clk_check()
2524 struct snd_soc_component *component = rt5682->component; in rt5682_wclk_prepare()
2529 return -EINVAL; in rt5682_wclk_prepare()
2560 struct snd_soc_component *component = rt5682->component; in rt5682_wclk_unprepare()
2571 if (!rt5682->jack_type) in rt5682_wclk_unprepare()
2590 struct snd_soc_component *component = rt5682->component; in rt5682_wclk_recalc_rate()
2598 if (rt5682->lrck[RT5682_AIF1] != CLK_48 && in rt5682_wclk_recalc_rate()
2599 rt5682->lrck[RT5682_AIF1] != CLK_44) { in rt5682_wclk_recalc_rate()
2600 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n", in rt5682_wclk_recalc_rate()
2605 return rt5682->lrck[RT5682_AIF1]; in rt5682_wclk_recalc_rate()
2614 struct snd_soc_component *component = rt5682->component; in rt5682_wclk_round_rate()
2618 return -EINVAL; in rt5682_wclk_round_rate()
2624 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n", in rt5682_wclk_round_rate()
2638 struct snd_soc_component *component = rt5682->component; in rt5682_wclk_set_rate()
2645 return -EINVAL; in rt5682_wclk_set_rate()
2656 dev_warn(component->dev, in rt5682_wclk_set_rate()
2661 dev_warn(component->dev, "clk %s only support %d Hz input\n", in rt5682_wclk_set_rate()
2675 rt5682->lrck[RT5682_AIF1] = rate; in rt5682_wclk_set_rate()
2677 pre_div = rl6231_get_clk_info(rt5682->sysclk, rate); in rt5682_wclk_set_rate()
2682 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); in rt5682_wclk_set_rate()
2693 struct snd_soc_component *component = rt5682->component; in rt5682_bclk_recalc_rate()
2737 return -EINVAL; in rt5682_bclk_round_rate()
2757 struct snd_soc_component *component = rt5682->component; in rt5682_bclk_set_rate()
2762 return -EINVAL; in rt5682_bclk_set_rate()
2767 if (dai->id == RT5682_AIF1) in rt5682_bclk_set_rate()
2770 dev_err(component->dev, "dai %d not found in component\n", in rt5682_bclk_set_rate()
2772 return -ENODEV; in rt5682_bclk_set_rate()
2795 struct device *dev = component->dev; in rt5682_register_dai_clks()
2797 struct rt5682_platform_data *pdata = &rt5682->pdata; in rt5682_register_dai_clks()
2804 dai_clk_hw = &rt5682->dai_clks_hw[i]; in rt5682_register_dai_clks()
2809 if (rt5682->mclk) { in rt5682_register_dai_clks()
2819 &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX] in rt5682_register_dai_clks()
2825 return -EINVAL; in rt5682_register_dai_clks()
2828 init.name = pdata->dai_clk_names[i]; in rt5682_register_dai_clks()
2831 dai_clk_hw->init = &init; in rt5682_register_dai_clks()
2840 if (dev->of_node) { in rt5682_register_dai_clks()
2861 struct snd_soc_dapm_context *dapm = &component->dapm; in rt5682_probe()
2866 rt5682->component = component; in rt5682_probe()
2868 if (rt5682->is_sdw) { in rt5682_probe()
2869 slave = rt5682->slave; in rt5682_probe()
2871 &slave->initialization_complete, in rt5682_probe()
2874 dev_err(&slave->dev, "Initialization not complete, timed out\n"); in rt5682_probe()
2875 return -ETIMEDOUT; in rt5682_probe()
2880 rt5682->mclk = devm_clk_get(component->dev, "mclk"); in rt5682_probe()
2881 if (IS_ERR(rt5682->mclk)) { in rt5682_probe()
2882 if (PTR_ERR(rt5682->mclk) != -ENOENT) { in rt5682_probe()
2883 ret = PTR_ERR(rt5682->mclk); in rt5682_probe()
2886 rt5682->mclk = NULL; in rt5682_probe()
2895 rt5682->lrck[RT5682_AIF1] = CLK_48; in rt5682_probe()
2918 if (rt5682->is_sdw) in rt5682_suspend()
2921 cancel_delayed_work_sync(&rt5682->jack_detect_work); in rt5682_suspend()
2922 cancel_delayed_work_sync(&rt5682->jd_check_work); in rt5682_suspend()
2923 if (rt5682->hs_jack && rt5682->jack_type == SND_JACK_HEADSET) { in rt5682_suspend()
2945 /* enter SAR ADC power saving mode */ in rt5682_suspend()
2954 regcache_cache_only(rt5682->regmap, true); in rt5682_suspend()
2955 regcache_mark_dirty(rt5682->regmap); in rt5682_suspend()
2963 if (rt5682->is_sdw) in rt5682_resume()
2966 regcache_cache_only(rt5682->regmap, false); in rt5682_resume()
2967 regcache_sync(rt5682->regmap); in rt5682_resume()
2969 if (rt5682->hs_jack && rt5682->jack_type == SND_JACK_HEADSET) { in rt5682_resume()
2981 &rt5682->jack_detect_work, msecs_to_jiffies(250)); in rt5682_resume()
3029 device_property_read_u32(dev, "realtek,dmic1-data-pin", in rt5682_parse_dt()
3030 &rt5682->pdata.dmic1_data_pin); in rt5682_parse_dt()
3031 device_property_read_u32(dev, "realtek,dmic1-clk-pin", in rt5682_parse_dt()
3032 &rt5682->pdata.dmic1_clk_pin); in rt5682_parse_dt()
3033 device_property_read_u32(dev, "realtek,jd-src", in rt5682_parse_dt()
3034 &rt5682->pdata.jd_src); in rt5682_parse_dt()
3035 device_property_read_u32(dev, "realtek,btndet-delay", in rt5682_parse_dt()
3036 &rt5682->pdata.btndet_delay); in rt5682_parse_dt()
3037 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz", in rt5682_parse_dt()
3038 &rt5682->pdata.dmic_clk_rate); in rt5682_parse_dt()
3039 device_property_read_u32(dev, "realtek,dmic-delay-ms", in rt5682_parse_dt()
3040 &rt5682->pdata.dmic_delay); in rt5682_parse_dt()
3042 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node, in rt5682_parse_dt()
3043 "realtek,ldo1-en-gpios", 0); in rt5682_parse_dt()
3045 if (device_property_read_string_array(dev, "clock-output-names", in rt5682_parse_dt()
3046 rt5682->pdata.dai_clk_names, in rt5682_parse_dt()
3049 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX], in rt5682_parse_dt()
3050 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]); in rt5682_parse_dt()
3052 rt5682->pdata.dmic_clk_driving_high = device_property_read_bool(dev, in rt5682_parse_dt()
3053 "realtek,dmic-clk-driving-high"); in rt5682_parse_dt()
3063 mutex_lock(&rt5682->calibrate_mutex); in rt5682_calibrate()
3066 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f); in rt5682_calibrate()
3067 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af); in rt5682_calibrate()
3069 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af); in rt5682_calibrate()
3070 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300); in rt5682_calibrate()
3071 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000); in rt5682_calibrate()
3072 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100); in rt5682_calibrate()
3073 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800); in rt5682_calibrate()
3074 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000); in rt5682_calibrate()
3075 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005); in rt5682_calibrate()
3076 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c); in rt5682_calibrate()
3077 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d); in rt5682_calibrate()
3078 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321); in rt5682_calibrate()
3079 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004); in rt5682_calibrate()
3080 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); in rt5682_calibrate()
3081 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1); in rt5682_calibrate()
3082 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311); in rt5682_calibrate()
3083 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); in rt5682_calibrate()
3085 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00); in rt5682_calibrate()
3088 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value); in rt5682_calibrate()
3096 dev_err(rt5682->component->dev, "HP Calibration Failure\n"); in rt5682_calibrate()
3099 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f); in rt5682_calibrate()
3100 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080); in rt5682_calibrate()
3101 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000); in rt5682_calibrate()
3102 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000); in rt5682_calibrate()
3103 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000); in rt5682_calibrate()
3104 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005); in rt5682_calibrate()
3105 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4); in rt5682_calibrate()
3106 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c); in rt5682_calibrate()
3108 mutex_unlock(&rt5682->calibrate_mutex); in rt5682_calibrate()