Lines Matching +full:mux +full:-
1 // SPDX-License-Identifier: GPL-2.0-only
3 * rt5665.c -- RT5665/RT5658 ALSA SoC audio codec driver
27 #include <sound/soc-dapm.h>
888 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
889 static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0);
890 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
891 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
892 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
893 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
895 static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
956 SOC_DAPM_ENUM("IF1_1 01 ADC Swap Mux", rt5665_if1_1_01_adc_enum);
959 SOC_DAPM_ENUM("IF1_1 23 ADC Swap Mux", rt5665_if1_1_23_adc_enum);
962 SOC_DAPM_ENUM("IF1_1 45 ADC Swap Mux", rt5665_if1_1_45_adc_enum);
965 SOC_DAPM_ENUM("IF1_1 67 ADC Swap Mux", rt5665_if1_1_67_adc_enum);
968 SOC_DAPM_ENUM("IF1_2 01 ADC Swap Mux", rt5665_if1_2_01_adc_enum);
971 SOC_DAPM_ENUM("IF1_2 23 ADC1 Swap Mux", rt5665_if1_2_23_adc_enum);
974 SOC_DAPM_ENUM("IF1_2 45 ADC1 Swap Mux", rt5665_if1_2_45_adc_enum);
977 SOC_DAPM_ENUM("IF1_2 67 ADC1 Swap Mux", rt5665_if1_2_67_adc_enum);
1030 * rt5665_sel_asrc_clk_src - select ASRC clock source for a set of filters
1062 return -EINVAL; in rt5665_sel_asrc_clk_src()
1159 * rt5665_headset_detect - Detect headset.
1177 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, in rt5665_headset_detect()
1180 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val); in rt5665_headset_detect()
1182 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1, in rt5665_headset_detect()
1185 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val); in rt5665_headset_detect()
1188 regmap_read(rt5665->regmap, RT5665_GPIO_STA, in rt5665_headset_detect()
1193 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1, in rt5665_headset_detect()
1195 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_3, 0x3424); in rt5665_headset_detect()
1196 regmap_write(rt5665->regmap, RT5665_IL_CMD_1, 0x0048); in rt5665_headset_detect()
1197 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0xa291); in rt5665_headset_detect()
1201 rt5665->sar_adc_value = snd_soc_component_read(rt5665->component, in rt5665_headset_detect()
1204 sar_hs_type = rt5665->pdata.sar_hs_type ? in rt5665_headset_detect()
1205 rt5665->pdata.sar_hs_type : 729; in rt5665_headset_detect()
1207 if (rt5665->sar_adc_value > sar_hs_type) { in rt5665_headset_detect()
1208 rt5665->jack_type = SND_JACK_HEADSET; in rt5665_headset_detect()
1211 rt5665->jack_type = SND_JACK_HEADPHONE; in rt5665_headset_detect()
1212 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, in rt5665_headset_detect()
1214 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, in rt5665_headset_detect()
1220 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0x2291); in rt5665_headset_detect()
1221 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, 0); in rt5665_headset_detect()
1224 if (rt5665->jack_type == SND_JACK_HEADSET) in rt5665_headset_detect()
1226 rt5665->jack_type = 0; in rt5665_headset_detect()
1229 dev_dbg(component->dev, "jack_type = %d\n", rt5665->jack_type); in rt5665_headset_detect()
1230 return rt5665->jack_type; in rt5665_headset_detect()
1238 &rt5665->jack_detect_work, msecs_to_jiffies(250)); in rt5665_irq()
1248 if (snd_soc_component_read(rt5665->component, RT5665_AJD1_CTRL) & 0x0010) { in rt5665_jd_check_handler()
1250 rt5665->jack_type = rt5665_headset_detect(rt5665->component, 0); in rt5665_jd_check_handler()
1252 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type, in rt5665_jd_check_handler()
1257 schedule_delayed_work(&rt5665->jd_check_work, 500); in rt5665_jd_check_handler()
1266 switch (rt5665->pdata.jd_src) { in rt5665_set_jack_detect()
1268 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1, in rt5665_set_jack_detect()
1270 regmap_update_bits(rt5665->regmap, RT5665_RC_CLK_CTRL, in rt5665_set_jack_detect()
1272 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_2, in rt5665_set_jack_detect()
1274 regmap_update_bits(rt5665->regmap, RT5665_IRQ_CTRL_1, 0x8, 0x8); in rt5665_set_jack_detect()
1281 dev_warn(component->dev, "Wrong JD source\n"); in rt5665_set_jack_detect()
1285 rt5665->hs_jack = hs_jack; in rt5665_set_jack_detect()
1296 while (!rt5665->component) { in rt5665_jack_detect_handler()
1301 while (!rt5665->component->card->instantiated) { in rt5665_jack_detect_handler()
1306 while (!rt5665->calibration_done) { in rt5665_jack_detect_handler()
1311 mutex_lock(&rt5665->calibrate_mutex); in rt5665_jack_detect_handler()
1313 val = snd_soc_component_read(rt5665->component, RT5665_AJD1_CTRL) & 0x0010; in rt5665_jack_detect_handler()
1316 if (rt5665->jack_type == 0) { in rt5665_jack_detect_handler()
1318 rt5665->jack_type = in rt5665_jack_detect_handler()
1319 rt5665_headset_detect(rt5665->component, 1); in rt5665_jack_detect_handler()
1322 rt5665->jack_type = SND_JACK_HEADSET; in rt5665_jack_detect_handler()
1323 btn_type = rt5665_button_detect(rt5665->component); in rt5665_jack_detect_handler()
1335 rt5665->jack_type |= SND_JACK_BTN_0; in rt5665_jack_detect_handler()
1340 rt5665->jack_type |= SND_JACK_BTN_1; in rt5665_jack_detect_handler()
1345 rt5665->jack_type |= SND_JACK_BTN_2; in rt5665_jack_detect_handler()
1350 rt5665->jack_type |= SND_JACK_BTN_3; in rt5665_jack_detect_handler()
1356 dev_err(rt5665->component->dev, in rt5665_jack_detect_handler()
1364 rt5665->jack_type = rt5665_headset_detect(rt5665->component, 0); in rt5665_jack_detect_handler()
1367 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type, in rt5665_jack_detect_handler()
1372 if (rt5665->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | in rt5665_jack_detect_handler()
1374 schedule_delayed_work(&rt5665->jd_check_work, 0); in rt5665_jack_detect_handler()
1376 cancel_delayed_work_sync(&rt5665->jd_check_work); in rt5665_jack_detect_handler()
1378 mutex_unlock(&rt5665->calibrate_mutex); in rt5665_jack_detect_handler()
1467 * set_dmic_clk - Set parameter of dmic.
1479 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in set_dmic_clk()
1483 pd = rl6231_get_pre_div(rt5665->regmap, in set_dmic_clk()
1485 idx = rl6231_calc_dmic_clk(rt5665->sysclk / pd); in set_dmic_clk()
1488 dev_err(component->dev, "Failed to set DMIC clock\n"); in set_dmic_clk()
1499 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5665_charge_pump_event()
1523 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in is_sys_clk_from_pll()
1537 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in is_using_asrc()
1539 switch (w->shift) { in is_using_asrc()
1838 /*MX-17 [6:4], MX-17 [2:0]*/
1858 /*MX-1B [6:4], MX-1B [2:0]*/
1878 /* MX-26 [13] [5] */
1880 "DD Mux", "ADC"
1898 /* MX-26 [11:10] [3:2] */
1918 /* MX-26 [12] [4] */
1938 /* MX-26 [8] */
1948 SOC_DAPM_ENUM("Stereo1 DMIC Mux", rt5665_sto1_dmic_enum);
1950 /* MX-26 [9] */
1962 /* MX-26 [1:0] */
1975 /* MX-27 [12] */
1989 /* MX-27 [13] */
1991 "DD Mux", "ADC"
2001 /* MX-27 [9][1]*/
2021 /* MX-27 [11:10], MX-27 [3:2] */
2041 /* MX-27 [8] */
2054 /* MX-27 [4] */
2067 /* MX-27 [5] */
2069 "DD Mux", "ADC"
2080 /* MX-27 [0] */
2094 /* MX-28 [13] [5] */
2096 "DD Mux", "ADC"
2114 /* MX-28 [11:10] [3:2] */
2134 /* MX-28 [12] [4] */
2154 /* MX-28 [8] */
2166 /* MX-28 [9] */
2178 /* MX-28 [1] */
2191 /* MX-29 [11:10], MX-29 [9:8]*/
2211 /* MX-2D [13:12], MX-2D [9:8]*/
2231 /* MX-2D [5:4], MX-2D [1:0]*/
2251 /* MX-2E [5:4], MX-2E [0]*/
2271 /* MX-2F [14:12] */
2284 /* MX-2F [6:4] */
2298 /* MX-30 [6:4] */
2312 /* MX-31 [11:10] [9:8] */
2333 /* MX-7a[10] */
2345 /* MX-7a[9] */
2357 /* MX-7a[8] */
2369 /* MX-7b[10] */
2381 /* MX-7b[9] */
2393 /* MX-7b[8] */
2405 /* MX-7b[7] */
2417 /* MX-7a[4:0] MX-7b[4:0] */
2430 SOC_DAPM_ENUM("TDM1 ADC Mux", rt5665_tdm1_adc_data_enum);
2474 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5665_mono_event()
2506 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5665_hp_event()
2532 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5665_lout_event()
2572 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5665_set_verf()
2576 switch (w->shift) { in rt5665_set_verf()
2599 switch (w->shift) { in rt5665_set_verf()
2630 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5665_i2s_pin_event()
2633 switch (w->shift) { in rt5665_i2s_pin_event()
2834 /* ADC Mux */
2835 SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2837 SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2839 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2841 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2843 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2845 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2847 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2849 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2851 SND_SOC_DAPM_MUX("Stereo1 DD L Mux", SND_SOC_NOPM, 0, 0,
2853 SND_SOC_DAPM_MUX("Stereo1 DD R Mux", SND_SOC_NOPM, 0, 0,
2855 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2857 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2859 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2861 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2863 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2865 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2867 SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
2869 SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
2871 SND_SOC_DAPM_MUX("Mono DD L Mux", SND_SOC_NOPM, 0, 0,
2873 SND_SOC_DAPM_MUX("Mono DD R Mux", SND_SOC_NOPM, 0, 0,
2875 SND_SOC_DAPM_MUX("Stereo2 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2877 SND_SOC_DAPM_MUX("Stereo2 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2879 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2881 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2883 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2885 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2887 SND_SOC_DAPM_MUX("Stereo2 ADC L Mux", SND_SOC_NOPM, 0, 0,
2889 SND_SOC_DAPM_MUX("Stereo2 ADC R Mux", SND_SOC_NOPM, 0, 0,
2891 SND_SOC_DAPM_MUX("Stereo2 DD L Mux", SND_SOC_NOPM, 0, 0,
2893 SND_SOC_DAPM_MUX("Stereo2 DD R Mux", SND_SOC_NOPM, 0, 0,
2967 SND_SOC_DAPM_MUX("IF1_1_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2969 SND_SOC_DAPM_MUX("IF1_1_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2971 SND_SOC_DAPM_MUX("IF1_1_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2974 SND_SOC_DAPM_MUX("IF1_2_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2976 SND_SOC_DAPM_MUX("IF1_2_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2978 SND_SOC_DAPM_MUX("IF1_2_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2980 SND_SOC_DAPM_MUX("IF1_2_ADC4 Mux", SND_SOC_NOPM, 0, 0,
2982 SND_SOC_DAPM_MUX("TDM1 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2984 SND_SOC_DAPM_MUX("TDM1 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2986 SND_SOC_DAPM_MUX("TDM1 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2988 SND_SOC_DAPM_MUX("TDM1 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2990 SND_SOC_DAPM_MUX("TDM2 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2992 SND_SOC_DAPM_MUX("TDM2 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2994 SND_SOC_DAPM_MUX("TDM2 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2996 SND_SOC_DAPM_MUX("TDM2 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2998 SND_SOC_DAPM_MUX("IF2_1 ADC Mux", SND_SOC_NOPM, 0, 0,
3000 SND_SOC_DAPM_MUX("IF2_2 ADC Mux", SND_SOC_NOPM, 0, 0,
3002 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
3004 SND_SOC_DAPM_MUX("IF1_1 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3006 SND_SOC_DAPM_MUX("IF1_1 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3008 SND_SOC_DAPM_MUX("IF1_1 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3010 SND_SOC_DAPM_MUX("IF1_1 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3012 SND_SOC_DAPM_MUX("IF1_1 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3014 SND_SOC_DAPM_MUX("IF1_1 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3016 SND_SOC_DAPM_MUX("IF1_1 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3018 SND_SOC_DAPM_MUX("IF1_1 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3020 SND_SOC_DAPM_MUX("IF1_2 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3022 SND_SOC_DAPM_MUX("IF1_2 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3024 SND_SOC_DAPM_MUX("IF1_2 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3026 SND_SOC_DAPM_MUX("IF1_2 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3028 SND_SOC_DAPM_MUX("IF1_2 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3030 SND_SOC_DAPM_MUX("IF1_2 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3032 SND_SOC_DAPM_MUX("IF1_2 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3034 SND_SOC_DAPM_MUX("IF1_2 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3036 SND_SOC_DAPM_MUX("IF2_1 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3038 SND_SOC_DAPM_MUX("IF2_1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3040 SND_SOC_DAPM_MUX("IF2_2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3042 SND_SOC_DAPM_MUX("IF2_2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3044 SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3046 SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3104 /* DAC channel Mux */
3105 SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l1_mux),
3106 SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r1_mux),
3107 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l2_mux),
3108 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r2_mux),
3109 SND_SOC_DAPM_MUX("DAC L3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l3_mux),
3110 SND_SOC_DAPM_MUX("DAC R3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r3_mux),
3217 SND_SOC_DAPM_MUX("PDM L Mux", SND_SOC_NOPM,
3219 SND_SOC_DAPM_MUX("PDM R Mux", SND_SOC_NOPM,
3277 {"Stereo1 DMIC L Mux", NULL, "DMIC STO1 ASRC"},
3278 {"Stereo1 DMIC R Mux", NULL, "DMIC STO1 ASRC"},
3279 {"Stereo2 DMIC L Mux", NULL, "DMIC STO2 ASRC"},
3280 {"Stereo2 DMIC R Mux", NULL, "DMIC STO2 ASRC"},
3281 {"Mono DMIC L Mux", NULL, "DMIC MONO L ASRC"},
3282 {"Mono DMIC R Mux", NULL, "DMIC MONO R ASRC"},
3387 {"Stereo1 DMIC L Mux", "DMIC1", "DMIC L1"},
3388 {"Stereo1 DMIC L Mux", "DMIC2", "DMIC L2"},
3390 {"Stereo1 DMIC R Mux", "DMIC1", "DMIC R1"},
3391 {"Stereo1 DMIC R Mux", "DMIC2", "DMIC R2"},
3393 {"Mono DMIC L Mux", "DMIC1 L", "DMIC L1"},
3394 {"Mono DMIC L Mux", "DMIC2 L", "DMIC L2"},
3396 {"Mono DMIC R Mux", "DMIC1 R", "DMIC R1"},
3397 {"Mono DMIC R Mux", "DMIC2 R", "DMIC R2"},
3399 {"Stereo2 DMIC L Mux", "DMIC1", "DMIC L1"},
3400 {"Stereo2 DMIC L Mux", "DMIC2", "DMIC L2"},
3402 {"Stereo2 DMIC R Mux", "DMIC1", "DMIC R1"},
3403 {"Stereo2 DMIC R Mux", "DMIC2", "DMIC R2"},
3405 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
3406 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
3407 {"Stereo1 ADC L Mux", "ADC2 L", "ADC2 L"},
3408 {"Stereo1 ADC L Mux", "ADC2 R", "ADC2 R"},
3409 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
3410 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
3411 {"Stereo1 ADC R Mux", "ADC2 L", "ADC2 L"},
3412 {"Stereo1 ADC R Mux", "ADC2 R", "ADC2 R"},
3414 {"Stereo1 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3415 {"Stereo1 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3417 {"Stereo1 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3418 {"Stereo1 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3420 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
3421 {"Stereo1 ADC L1 Mux", "DD Mux", "Stereo1 DD L Mux"},
3422 {"Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux"},
3423 {"Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3425 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
3426 {"Stereo1 ADC R1 Mux", "DD Mux", "Stereo1 DD R Mux"},
3427 {"Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux"},
3428 {"Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3430 {"Mono ADC L Mux", "ADC1 L", "ADC1 L"},
3431 {"Mono ADC L Mux", "ADC1 R", "ADC1 R"},
3432 {"Mono ADC L Mux", "ADC2 L", "ADC2 L"},
3433 {"Mono ADC L Mux", "ADC2 R", "ADC2 R"},
3435 {"Mono ADC R Mux", "ADC1 L", "ADC1 L"},
3436 {"Mono ADC R Mux", "ADC1 R", "ADC1 R"},
3437 {"Mono ADC R Mux", "ADC2 L", "ADC2 L"},
3438 {"Mono ADC R Mux", "ADC2 R", "ADC2 R"},
3440 {"Mono DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3441 {"Mono DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3443 {"Mono DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3444 {"Mono DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3446 {"Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux"},
3447 {"Mono ADC L2 Mux", "DAC MIXL", "DAC MIXL"},
3448 {"Mono ADC L1 Mux", "DD Mux", "Mono DD L Mux"},
3449 {"Mono ADC L1 Mux", "ADC", "Mono ADC L Mux"},
3451 {"Mono ADC R1 Mux", "DD Mux", "Mono DD R Mux"},
3452 {"Mono ADC R1 Mux", "ADC", "Mono ADC R Mux"},
3453 {"Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux"},
3454 {"Mono ADC R2 Mux", "DAC MIXR", "DAC MIXR"},
3456 {"Stereo2 ADC L Mux", "ADC1 L", "ADC1 L"},
3457 {"Stereo2 ADC L Mux", "ADC2 L", "ADC2 L"},
3458 {"Stereo2 ADC L Mux", "ADC1 R", "ADC1 R"},
3459 {"Stereo2 ADC R Mux", "ADC1 L", "ADC1 L"},
3460 {"Stereo2 ADC R Mux", "ADC2 L", "ADC2 L"},
3461 {"Stereo2 ADC R Mux", "ADC1 R", "ADC1 R"},
3463 {"Stereo2 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3464 {"Stereo2 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3466 {"Stereo2 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3467 {"Stereo2 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3469 {"Stereo2 ADC L1 Mux", "ADC", "Stereo2 ADC L Mux"},
3470 {"Stereo2 ADC L1 Mux", "DD Mux", "Stereo2 DD L Mux"},
3471 {"Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC L Mux"},
3472 {"Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3474 {"Stereo2 ADC R1 Mux", "ADC", "Stereo2 ADC R Mux"},
3475 {"Stereo2 ADC R1 Mux", "DD Mux", "Stereo2 DD R Mux"},
3476 {"Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC R Mux"},
3477 {"Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3479 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
3480 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
3483 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
3484 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
3487 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
3488 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
3491 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
3492 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
3495 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
3496 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
3499 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
3500 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
3510 {"IF1_1_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3511 {"IF1_1_ADC1 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3512 {"IF1_1_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3513 {"IF1_1_ADC2 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3514 {"IF1_1_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3515 {"IF1_1_ADC3 Mux", "IF3 DAC", "IF3 DAC"},
3518 {"IF1_2_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3519 {"IF1_2_ADC1 Mux", "IF1 DAC", "IF1 DAC1"},
3520 {"IF1_2_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3521 {"IF1_2_ADC2 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3522 {"IF1_2_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3523 {"IF1_2_ADC3 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3524 {"IF1_2_ADC4 Mux", "DAC1", "DAC1 MIX"},
3525 {"IF1_2_ADC4 Mux", "IF3 DAC", "IF3 DAC"},
3527 {"TDM1 slot 01 Data Mux", "1234", "IF1_1_ADC1 Mux"},
3528 {"TDM1 slot 01 Data Mux", "1243", "IF1_1_ADC1 Mux"},
3529 {"TDM1 slot 01 Data Mux", "1324", "IF1_1_ADC1 Mux"},
3530 {"TDM1 slot 01 Data Mux", "1342", "IF1_1_ADC1 Mux"},
3531 {"TDM1 slot 01 Data Mux", "1432", "IF1_1_ADC1 Mux"},
3532 {"TDM1 slot 01 Data Mux", "1423", "IF1_1_ADC1 Mux"},
3533 {"TDM1 slot 01 Data Mux", "2134", "IF1_1_ADC2 Mux"},
3534 {"TDM1 slot 01 Data Mux", "2143", "IF1_1_ADC2 Mux"},
3535 {"TDM1 slot 01 Data Mux", "2314", "IF1_1_ADC2 Mux"},
3536 {"TDM1 slot 01 Data Mux", "2341", "IF1_1_ADC2 Mux"},
3537 {"TDM1 slot 01 Data Mux", "2431", "IF1_1_ADC2 Mux"},
3538 {"TDM1 slot 01 Data Mux", "2413", "IF1_1_ADC2 Mux"},
3539 {"TDM1 slot 01 Data Mux", "3124", "IF1_1_ADC3 Mux"},
3540 {"TDM1 slot 01 Data Mux", "3142", "IF1_1_ADC3 Mux"},
3541 {"TDM1 slot 01 Data Mux", "3214", "IF1_1_ADC3 Mux"},
3542 {"TDM1 slot 01 Data Mux", "3241", "IF1_1_ADC3 Mux"},
3543 {"TDM1 slot 01 Data Mux", "3412", "IF1_1_ADC3 Mux"},
3544 {"TDM1 slot 01 Data Mux", "3421", "IF1_1_ADC3 Mux"},
3545 {"TDM1 slot 01 Data Mux", "4123", "IF1_1_ADC4"},
3546 {"TDM1 slot 01 Data Mux", "4132", "IF1_1_ADC4"},
3547 {"TDM1 slot 01 Data Mux", "4213", "IF1_1_ADC4"},
3548 {"TDM1 slot 01 Data Mux", "4231", "IF1_1_ADC4"},
3549 {"TDM1 slot 01 Data Mux", "4312", "IF1_1_ADC4"},
3550 {"TDM1 slot 01 Data Mux", "4321", "IF1_1_ADC4"},
3551 {"TDM1 slot 01 Data Mux", NULL, "I2S1_1"},
3553 {"TDM1 slot 23 Data Mux", "1234", "IF1_1_ADC2 Mux"},
3554 {"TDM1 slot 23 Data Mux", "1243", "IF1_1_ADC2 Mux"},
3555 {"TDM1 slot 23 Data Mux", "1324", "IF1_1_ADC3 Mux"},
3556 {"TDM1 slot 23 Data Mux", "1342", "IF1_1_ADC3 Mux"},
3557 {"TDM1 slot 23 Data Mux", "1432", "IF1_1_ADC4"},
3558 {"TDM1 slot 23 Data Mux", "1423", "IF1_1_ADC4"},
3559 {"TDM1 slot 23 Data Mux", "2134", "IF1_1_ADC1 Mux"},
3560 {"TDM1 slot 23 Data Mux", "2143", "IF1_1_ADC1 Mux"},
3561 {"TDM1 slot 23 Data Mux", "2314", "IF1_1_ADC3 Mux"},
3562 {"TDM1 slot 23 Data Mux", "2341", "IF1_1_ADC3 Mux"},
3563 {"TDM1 slot 23 Data Mux", "2431", "IF1_1_ADC4"},
3564 {"TDM1 slot 23 Data Mux", "2413", "IF1_1_ADC4"},
3565 {"TDM1 slot 23 Data Mux", "3124", "IF1_1_ADC1 Mux"},
3566 {"TDM1 slot 23 Data Mux", "3142", "IF1_1_ADC1 Mux"},
3567 {"TDM1 slot 23 Data Mux", "3214", "IF1_1_ADC2 Mux"},
3568 {"TDM1 slot 23 Data Mux", "3241", "IF1_1_ADC2 Mux"},
3569 {"TDM1 slot 23 Data Mux", "3412", "IF1_1_ADC4"},
3570 {"TDM1 slot 23 Data Mux", "3421", "IF1_1_ADC4"},
3571 {"TDM1 slot 23 Data Mux", "4123", "IF1_1_ADC1 Mux"},
3572 {"TDM1 slot 23 Data Mux", "4132", "IF1_1_ADC1 Mux"},
3573 {"TDM1 slot 23 Data Mux", "4213", "IF1_1_ADC2 Mux"},
3574 {"TDM1 slot 23 Data Mux", "4231", "IF1_1_ADC2 Mux"},
3575 {"TDM1 slot 23 Data Mux", "4312", "IF1_1_ADC3 Mux"},
3576 {"TDM1 slot 23 Data Mux", "4321", "IF1_1_ADC3 Mux"},
3577 {"TDM1 slot 23 Data Mux", NULL, "I2S1_1"},
3579 {"TDM1 slot 45 Data Mux", "1234", "IF1_1_ADC3 Mux"},
3580 {"TDM1 slot 45 Data Mux", "1243", "IF1_1_ADC4"},
3581 {"TDM1 slot 45 Data Mux", "1324", "IF1_1_ADC2 Mux"},
3582 {"TDM1 slot 45 Data Mux", "1342", "IF1_1_ADC4"},
3583 {"TDM1 slot 45 Data Mux", "1432", "IF1_1_ADC3 Mux"},
3584 {"TDM1 slot 45 Data Mux", "1423", "IF1_1_ADC2 Mux"},
3585 {"TDM1 slot 45 Data Mux", "2134", "IF1_1_ADC3 Mux"},
3586 {"TDM1 slot 45 Data Mux", "2143", "IF1_1_ADC4"},
3587 {"TDM1 slot 45 Data Mux", "2314", "IF1_1_ADC1 Mux"},
3588 {"TDM1 slot 45 Data Mux", "2341", "IF1_1_ADC4"},
3589 {"TDM1 slot 45 Data Mux", "2431", "IF1_1_ADC3 Mux"},
3590 {"TDM1 slot 45 Data Mux", "2413", "IF1_1_ADC1 Mux"},
3591 {"TDM1 slot 45 Data Mux", "3124", "IF1_1_ADC2 Mux"},
3592 {"TDM1 slot 45 Data Mux", "3142", "IF1_1_ADC4"},
3593 {"TDM1 slot 45 Data Mux", "3214", "IF1_1_ADC1 Mux"},
3594 {"TDM1 slot 45 Data Mux", "3241", "IF1_1_ADC4"},
3595 {"TDM1 slot 45 Data Mux", "3412", "IF1_1_ADC1 Mux"},
3596 {"TDM1 slot 45 Data Mux", "3421", "IF1_1_ADC2 Mux"},
3597 {"TDM1 slot 45 Data Mux", "4123", "IF1_1_ADC2 Mux"},
3598 {"TDM1 slot 45 Data Mux", "4132", "IF1_1_ADC3 Mux"},
3599 {"TDM1 slot 45 Data Mux", "4213", "IF1_1_ADC1 Mux"},
3600 {"TDM1 slot 45 Data Mux", "4231", "IF1_1_ADC3 Mux"},
3601 {"TDM1 slot 45 Data Mux", "4312", "IF1_1_ADC1 Mux"},
3602 {"TDM1 slot 45 Data Mux", "4321", "IF1_1_ADC2 Mux"},
3603 {"TDM1 slot 45 Data Mux", NULL, "I2S1_1"},
3605 {"TDM1 slot 67 Data Mux", "1234", "IF1_1_ADC4"},
3606 {"TDM1 slot 67 Data Mux", "1243", "IF1_1_ADC3 Mux"},
3607 {"TDM1 slot 67 Data Mux", "1324", "IF1_1_ADC4"},
3608 {"TDM1 slot 67 Data Mux", "1342", "IF1_1_ADC2 Mux"},
3609 {"TDM1 slot 67 Data Mux", "1432", "IF1_1_ADC2 Mux"},
3610 {"TDM1 slot 67 Data Mux", "1423", "IF1_1_ADC3 Mux"},
3611 {"TDM1 slot 67 Data Mux", "2134", "IF1_1_ADC4"},
3612 {"TDM1 slot 67 Data Mux", "2143", "IF1_1_ADC3 Mux"},
3613 {"TDM1 slot 67 Data Mux", "2314", "IF1_1_ADC4"},
3614 {"TDM1 slot 67 Data Mux", "2341", "IF1_1_ADC1 Mux"},
3615 {"TDM1 slot 67 Data Mux", "2431", "IF1_1_ADC1 Mux"},
3616 {"TDM1 slot 67 Data Mux", "2413", "IF1_1_ADC3 Mux"},
3617 {"TDM1 slot 67 Data Mux", "3124", "IF1_1_ADC4"},
3618 {"TDM1 slot 67 Data Mux", "3142", "IF1_1_ADC2 Mux"},
3619 {"TDM1 slot 67 Data Mux", "3214", "IF1_1_ADC4"},
3620 {"TDM1 slot 67 Data Mux", "3241", "IF1_1_ADC1 Mux"},
3621 {"TDM1 slot 67 Data Mux", "3412", "IF1_1_ADC2 Mux"},
3622 {"TDM1 slot 67 Data Mux", "3421", "IF1_1_ADC1 Mux"},
3623 {"TDM1 slot 67 Data Mux", "4123", "IF1_1_ADC3 Mux"},
3624 {"TDM1 slot 67 Data Mux", "4132", "IF1_1_ADC2 Mux"},
3625 {"TDM1 slot 67 Data Mux", "4213", "IF1_1_ADC3 Mux"},
3626 {"TDM1 slot 67 Data Mux", "4231", "IF1_1_ADC1 Mux"},
3627 {"TDM1 slot 67 Data Mux", "4312", "IF1_1_ADC2 Mux"},
3628 {"TDM1 slot 67 Data Mux", "4321", "IF1_1_ADC1 Mux"},
3629 {"TDM1 slot 67 Data Mux", NULL, "I2S1_1"},
3632 {"TDM2 slot 01 Data Mux", "1234", "IF1_2_ADC1 Mux"},
3633 {"TDM2 slot 01 Data Mux", "1243", "IF1_2_ADC1 Mux"},
3634 {"TDM2 slot 01 Data Mux", "1324", "IF1_2_ADC1 Mux"},
3635 {"TDM2 slot 01 Data Mux", "1342", "IF1_2_ADC1 Mux"},
3636 {"TDM2 slot 01 Data Mux", "1432", "IF1_2_ADC1 Mux"},
3637 {"TDM2 slot 01 Data Mux", "1423", "IF1_2_ADC1 Mux"},
3638 {"TDM2 slot 01 Data Mux", "2134", "IF1_2_ADC2 Mux"},
3639 {"TDM2 slot 01 Data Mux", "2143", "IF1_2_ADC2 Mux"},
3640 {"TDM2 slot 01 Data Mux", "2314", "IF1_2_ADC2 Mux"},
3641 {"TDM2 slot 01 Data Mux", "2341", "IF1_2_ADC2 Mux"},
3642 {"TDM2 slot 01 Data Mux", "2431", "IF1_2_ADC2 Mux"},
3643 {"TDM2 slot 01 Data Mux", "2413", "IF1_2_ADC2 Mux"},
3644 {"TDM2 slot 01 Data Mux", "3124", "IF1_2_ADC3 Mux"},
3645 {"TDM2 slot 01 Data Mux", "3142", "IF1_2_ADC3 Mux"},
3646 {"TDM2 slot 01 Data Mux", "3214", "IF1_2_ADC3 Mux"},
3647 {"TDM2 slot 01 Data Mux", "3241", "IF1_2_ADC3 Mux"},
3648 {"TDM2 slot 01 Data Mux", "3412", "IF1_2_ADC3 Mux"},
3649 {"TDM2 slot 01 Data Mux", "3421", "IF1_2_ADC3 Mux"},
3650 {"TDM2 slot 01 Data Mux", "4123", "IF1_2_ADC4 Mux"},
3651 {"TDM2 slot 01 Data Mux", "4132", "IF1_2_ADC4 Mux"},
3652 {"TDM2 slot 01 Data Mux", "4213", "IF1_2_ADC4 Mux"},
3653 {"TDM2 slot 01 Data Mux", "4231", "IF1_2_ADC4 Mux"},
3654 {"TDM2 slot 01 Data Mux", "4312", "IF1_2_ADC4 Mux"},
3655 {"TDM2 slot 01 Data Mux", "4321", "IF1_2_ADC4 Mux"},
3656 {"TDM2 slot 01 Data Mux", NULL, "I2S1_2"},
3658 {"TDM2 slot 23 Data Mux", "1234", "IF1_2_ADC2 Mux"},
3659 {"TDM2 slot 23 Data Mux", "1243", "IF1_2_ADC2 Mux"},
3660 {"TDM2 slot 23 Data Mux", "1324", "IF1_2_ADC3 Mux"},
3661 {"TDM2 slot 23 Data Mux", "1342", "IF1_2_ADC3 Mux"},
3662 {"TDM2 slot 23 Data Mux", "1432", "IF1_2_ADC4 Mux"},
3663 {"TDM2 slot 23 Data Mux", "1423", "IF1_2_ADC4 Mux"},
3664 {"TDM2 slot 23 Data Mux", "2134", "IF1_2_ADC1 Mux"},
3665 {"TDM2 slot 23 Data Mux", "2143", "IF1_2_ADC1 Mux"},
3666 {"TDM2 slot 23 Data Mux", "2314", "IF1_2_ADC3 Mux"},
3667 {"TDM2 slot 23 Data Mux", "2341", "IF1_2_ADC3 Mux"},
3668 {"TDM2 slot 23 Data Mux", "2431", "IF1_2_ADC4 Mux"},
3669 {"TDM2 slot 23 Data Mux", "2413", "IF1_2_ADC4 Mux"},
3670 {"TDM2 slot 23 Data Mux", "3124", "IF1_2_ADC1 Mux"},
3671 {"TDM2 slot 23 Data Mux", "3142", "IF1_2_ADC1 Mux"},
3672 {"TDM2 slot 23 Data Mux", "3214", "IF1_2_ADC2 Mux"},
3673 {"TDM2 slot 23 Data Mux", "3241", "IF1_2_ADC2 Mux"},
3674 {"TDM2 slot 23 Data Mux", "3412", "IF1_2_ADC4 Mux"},
3675 {"TDM2 slot 23 Data Mux", "3421", "IF1_2_ADC4 Mux"},
3676 {"TDM2 slot 23 Data Mux", "4123", "IF1_2_ADC1 Mux"},
3677 {"TDM2 slot 23 Data Mux", "4132", "IF1_2_ADC1 Mux"},
3678 {"TDM2 slot 23 Data Mux", "4213", "IF1_2_ADC2 Mux"},
3679 {"TDM2 slot 23 Data Mux", "4231", "IF1_2_ADC2 Mux"},
3680 {"TDM2 slot 23 Data Mux", "4312", "IF1_2_ADC3 Mux"},
3681 {"TDM2 slot 23 Data Mux", "4321", "IF1_2_ADC3 Mux"},
3682 {"TDM2 slot 23 Data Mux", NULL, "I2S1_2"},
3684 {"TDM2 slot 45 Data Mux", "1234", "IF1_2_ADC3 Mux"},
3685 {"TDM2 slot 45 Data Mux", "1243", "IF1_2_ADC4 Mux"},
3686 {"TDM2 slot 45 Data Mux", "1324", "IF1_2_ADC2 Mux"},
3687 {"TDM2 slot 45 Data Mux", "1342", "IF1_2_ADC4 Mux"},
3688 {"TDM2 slot 45 Data Mux", "1432", "IF1_2_ADC3 Mux"},
3689 {"TDM2 slot 45 Data Mux", "1423", "IF1_2_ADC2 Mux"},
3690 {"TDM2 slot 45 Data Mux", "2134", "IF1_2_ADC3 Mux"},
3691 {"TDM2 slot 45 Data Mux", "2143", "IF1_2_ADC4 Mux"},
3692 {"TDM2 slot 45 Data Mux", "2314", "IF1_2_ADC1 Mux"},
3693 {"TDM2 slot 45 Data Mux", "2341", "IF1_2_ADC4 Mux"},
3694 {"TDM2 slot 45 Data Mux", "2431", "IF1_2_ADC3 Mux"},
3695 {"TDM2 slot 45 Data Mux", "2413", "IF1_2_ADC1 Mux"},
3696 {"TDM2 slot 45 Data Mux", "3124", "IF1_2_ADC2 Mux"},
3697 {"TDM2 slot 45 Data Mux", "3142", "IF1_2_ADC4 Mux"},
3698 {"TDM2 slot 45 Data Mux", "3214", "IF1_2_ADC1 Mux"},
3699 {"TDM2 slot 45 Data Mux", "3241", "IF1_2_ADC4 Mux"},
3700 {"TDM2 slot 45 Data Mux", "3412", "IF1_2_ADC1 Mux"},
3701 {"TDM2 slot 45 Data Mux", "3421", "IF1_2_ADC2 Mux"},
3702 {"TDM2 slot 45 Data Mux", "4123", "IF1_2_ADC2 Mux"},
3703 {"TDM2 slot 45 Data Mux", "4132", "IF1_2_ADC3 Mux"},
3704 {"TDM2 slot 45 Data Mux", "4213", "IF1_2_ADC1 Mux"},
3705 {"TDM2 slot 45 Data Mux", "4231", "IF1_2_ADC3 Mux"},
3706 {"TDM2 slot 45 Data Mux", "4312", "IF1_2_ADC1 Mux"},
3707 {"TDM2 slot 45 Data Mux", "4321", "IF1_2_ADC2 Mux"},
3708 {"TDM2 slot 45 Data Mux", NULL, "I2S1_2"},
3710 {"TDM2 slot 67 Data Mux", "1234", "IF1_2_ADC4 Mux"},
3711 {"TDM2 slot 67 Data Mux", "1243", "IF1_2_ADC3 Mux"},
3712 {"TDM2 slot 67 Data Mux", "1324", "IF1_2_ADC4 Mux"},
3713 {"TDM2 slot 67 Data Mux", "1342", "IF1_2_ADC2 Mux"},
3714 {"TDM2 slot 67 Data Mux", "1432", "IF1_2_ADC2 Mux"},
3715 {"TDM2 slot 67 Data Mux", "1423", "IF1_2_ADC3 Mux"},
3716 {"TDM2 slot 67 Data Mux", "2134", "IF1_2_ADC4 Mux"},
3717 {"TDM2 slot 67 Data Mux", "2143", "IF1_2_ADC3 Mux"},
3718 {"TDM2 slot 67 Data Mux", "2314", "IF1_2_ADC4 Mux"},
3719 {"TDM2 slot 67 Data Mux", "2341", "IF1_2_ADC1 Mux"},
3720 {"TDM2 slot 67 Data Mux", "2431", "IF1_2_ADC1 Mux"},
3721 {"TDM2 slot 67 Data Mux", "2413", "IF1_2_ADC3 Mux"},
3722 {"TDM2 slot 67 Data Mux", "3124", "IF1_2_ADC4 Mux"},
3723 {"TDM2 slot 67 Data Mux", "3142", "IF1_2_ADC2 Mux"},
3724 {"TDM2 slot 67 Data Mux", "3214", "IF1_2_ADC4 Mux"},
3725 {"TDM2 slot 67 Data Mux", "3241", "IF1_2_ADC1 Mux"},
3726 {"TDM2 slot 67 Data Mux", "3412", "IF1_2_ADC2 Mux"},
3727 {"TDM2 slot 67 Data Mux", "3421", "IF1_2_ADC1 Mux"},
3728 {"TDM2 slot 67 Data Mux", "4123", "IF1_2_ADC3 Mux"},
3729 {"TDM2 slot 67 Data Mux", "4132", "IF1_2_ADC2 Mux"},
3730 {"TDM2 slot 67 Data Mux", "4213", "IF1_2_ADC3 Mux"},
3731 {"TDM2 slot 67 Data Mux", "4231", "IF1_2_ADC1 Mux"},
3732 {"TDM2 slot 67 Data Mux", "4312", "IF1_2_ADC2 Mux"},
3733 {"TDM2 slot 67 Data Mux", "4321", "IF1_2_ADC1 Mux"},
3734 {"TDM2 slot 67 Data Mux", NULL, "I2S1_2"},
3736 {"IF1_1 0 ADC Swap Mux", "L/R", "TDM1 slot 01 Data Mux"},
3737 {"IF1_1 0 ADC Swap Mux", "L/L", "TDM1 slot 01 Data Mux"},
3738 {"IF1_1 1 ADC Swap Mux", "R/L", "TDM1 slot 01 Data Mux"},
3739 {"IF1_1 1 ADC Swap Mux", "R/R", "TDM1 slot 01 Data Mux"},
3740 {"IF1_1 2 ADC Swap Mux", "L/R", "TDM1 slot 23 Data Mux"},
3741 {"IF1_1 2 ADC Swap Mux", "R/L", "TDM1 slot 23 Data Mux"},
3742 {"IF1_1 3 ADC Swap Mux", "L/L", "TDM1 slot 23 Data Mux"},
3743 {"IF1_1 3 ADC Swap Mux", "R/R", "TDM1 slot 23 Data Mux"},
3744 {"IF1_1 4 ADC Swap Mux", "L/R", "TDM1 slot 45 Data Mux"},
3745 {"IF1_1 4 ADC Swap Mux", "R/L", "TDM1 slot 45 Data Mux"},
3746 {"IF1_1 5 ADC Swap Mux", "L/L", "TDM1 slot 45 Data Mux"},
3747 {"IF1_1 5 ADC Swap Mux", "R/R", "TDM1 slot 45 Data Mux"},
3748 {"IF1_1 6 ADC Swap Mux", "L/R", "TDM1 slot 67 Data Mux"},
3749 {"IF1_1 6 ADC Swap Mux", "R/L", "TDM1 slot 67 Data Mux"},
3750 {"IF1_1 7 ADC Swap Mux", "L/L", "TDM1 slot 67 Data Mux"},
3751 {"IF1_1 7 ADC Swap Mux", "R/R", "TDM1 slot 67 Data Mux"},
3752 {"IF1_2 0 ADC Swap Mux", "L/R", "TDM2 slot 01 Data Mux"},
3753 {"IF1_2 0 ADC Swap Mux", "R/L", "TDM2 slot 01 Data Mux"},
3754 {"IF1_2 1 ADC Swap Mux", "L/L", "TDM2 slot 01 Data Mux"},
3755 {"IF1_2 1 ADC Swap Mux", "R/R", "TDM2 slot 01 Data Mux"},
3756 {"IF1_2 2 ADC Swap Mux", "L/R", "TDM2 slot 23 Data Mux"},
3757 {"IF1_2 2 ADC Swap Mux", "R/L", "TDM2 slot 23 Data Mux"},
3758 {"IF1_2 3 ADC Swap Mux", "L/L", "TDM2 slot 23 Data Mux"},
3759 {"IF1_2 3 ADC Swap Mux", "R/R", "TDM2 slot 23 Data Mux"},
3760 {"IF1_2 4 ADC Swap Mux", "L/R", "TDM2 slot 45 Data Mux"},
3761 {"IF1_2 4 ADC Swap Mux", "R/L", "TDM2 slot 45 Data Mux"},
3762 {"IF1_2 5 ADC Swap Mux", "L/L", "TDM2 slot 45 Data Mux"},
3763 {"IF1_2 5 ADC Swap Mux", "R/R", "TDM2 slot 45 Data Mux"},
3764 {"IF1_2 6 ADC Swap Mux", "L/R", "TDM2 slot 67 Data Mux"},
3765 {"IF1_2 6 ADC Swap Mux", "R/L", "TDM2 slot 67 Data Mux"},
3766 {"IF1_2 7 ADC Swap Mux", "L/L", "TDM2 slot 67 Data Mux"},
3767 {"IF1_2 7 ADC Swap Mux", "R/R", "TDM2 slot 67 Data Mux"},
3769 {"IF2_1 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3770 {"IF2_1 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3771 {"IF2_1 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3772 {"IF2_1 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3773 {"IF2_1 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3774 {"IF2_1 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3775 {"IF2_1 ADC Mux", "IF3 DAC", "IF3 DAC"},
3776 {"IF2_1 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3777 {"IF2_1 ADC", NULL, "IF2_1 ADC Mux"},
3780 {"IF2_2 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3781 {"IF2_2 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3782 {"IF2_2 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3783 {"IF2_2 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3784 {"IF2_2 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3785 {"IF2_2 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3786 {"IF2_2 ADC Mux", "IF3 DAC", "IF3 DAC"},
3787 {"IF2_2 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3788 {"IF2_2 ADC", NULL, "IF2_2 ADC Mux"},
3791 {"IF3 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3792 {"IF3 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3793 {"IF3 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3794 {"IF3 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3795 {"IF3 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3796 {"IF3 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3797 {"IF3 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3798 {"IF3 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3799 {"IF3 ADC", NULL, "IF3 ADC Mux"},
3802 {"AIF1_1TX slot 0", NULL, "IF1_1 0 ADC Swap Mux"},
3803 {"AIF1_1TX slot 1", NULL, "IF1_1 1 ADC Swap Mux"},
3804 {"AIF1_1TX slot 2", NULL, "IF1_1 2 ADC Swap Mux"},
3805 {"AIF1_1TX slot 3", NULL, "IF1_1 3 ADC Swap Mux"},
3806 {"AIF1_1TX slot 4", NULL, "IF1_1 4 ADC Swap Mux"},
3807 {"AIF1_1TX slot 5", NULL, "IF1_1 5 ADC Swap Mux"},
3808 {"AIF1_1TX slot 6", NULL, "IF1_1 6 ADC Swap Mux"},
3809 {"AIF1_1TX slot 7", NULL, "IF1_1 7 ADC Swap Mux"},
3810 {"AIF1_2TX slot 0", NULL, "IF1_2 0 ADC Swap Mux"},
3811 {"AIF1_2TX slot 1", NULL, "IF1_2 1 ADC Swap Mux"},
3812 {"AIF1_2TX slot 2", NULL, "IF1_2 2 ADC Swap Mux"},
3813 {"AIF1_2TX slot 3", NULL, "IF1_2 3 ADC Swap Mux"},
3814 {"AIF1_2TX slot 4", NULL, "IF1_2 4 ADC Swap Mux"},
3815 {"AIF1_2TX slot 5", NULL, "IF1_2 5 ADC Swap Mux"},
3816 {"AIF1_2TX slot 6", NULL, "IF1_2 6 ADC Swap Mux"},
3817 {"AIF1_2TX slot 7", NULL, "IF1_2 7 ADC Swap Mux"},
3818 {"IF2_1 ADC Swap Mux", "L/R", "IF2_1 ADC"},
3819 {"IF2_1 ADC Swap Mux", "R/L", "IF2_1 ADC"},
3820 {"IF2_1 ADC Swap Mux", "L/L", "IF2_1 ADC"},
3821 {"IF2_1 ADC Swap Mux", "R/R", "IF2_1 ADC"},
3822 {"AIF2_1TX", NULL, "IF2_1 ADC Swap Mux"},
3823 {"IF2_2 ADC Swap Mux", "L/R", "IF2_2 ADC"},
3824 {"IF2_2 ADC Swap Mux", "R/L", "IF2_2 ADC"},
3825 {"IF2_2 ADC Swap Mux", "L/L", "IF2_2 ADC"},
3826 {"IF2_2 ADC Swap Mux", "R/R", "IF2_2 ADC"},
3827 {"AIF2_2TX", NULL, "IF2_2 ADC Swap Mux"},
3828 {"IF3 ADC Swap Mux", "L/R", "IF3 ADC"},
3829 {"IF3 ADC Swap Mux", "R/L", "IF3 ADC"},
3830 {"IF3 ADC Swap Mux", "L/L", "IF3 ADC"},
3831 {"IF3 ADC Swap Mux", "R/R", "IF3 ADC"},
3832 {"AIF3TX", NULL, "IF3 ADC Swap Mux"},
3837 {"IF2_1 DAC Swap Mux", "L/R", "AIF2_1RX"},
3838 {"IF2_1 DAC Swap Mux", "R/L", "AIF2_1RX"},
3839 {"IF2_1 DAC Swap Mux", "L/L", "AIF2_1RX"},
3840 {"IF2_1 DAC Swap Mux", "R/R", "AIF2_1RX"},
3841 {"IF2_2 DAC Swap Mux", "L/R", "AIF2_2RX"},
3842 {"IF2_2 DAC Swap Mux", "R/L", "AIF2_2RX"},
3843 {"IF2_2 DAC Swap Mux", "L/L", "AIF2_2RX"},
3844 {"IF2_2 DAC Swap Mux", "R/R", "AIF2_2RX"},
3845 {"IF2_1 DAC", NULL, "IF2_1 DAC Swap Mux"},
3846 {"IF2_2 DAC", NULL, "IF2_2 DAC Swap Mux"},
3847 {"IF3 DAC Swap Mux", "L/R", "AIF3RX"},
3848 {"IF3 DAC Swap Mux", "R/L", "AIF3RX"},
3849 {"IF3 DAC Swap Mux", "L/L", "AIF3RX"},
3850 {"IF3 DAC Swap Mux", "R/R", "AIF3RX"},
3851 {"IF3 DAC", NULL, "IF3 DAC Swap Mux"},
3873 {"DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L"},
3874 {"DAC L1 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3875 {"DAC L1 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3876 {"DAC L1 Mux", "IF3 DAC", "IF3 DAC L"},
3877 {"DAC L1 Mux", NULL, "DAC Stereo1 Filter"},
3879 {"DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R"},
3880 {"DAC R1 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3881 {"DAC R1 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3882 {"DAC R1 Mux", "IF3 DAC", "IF3 DAC R"},
3883 {"DAC R1 Mux", NULL, "DAC Stereo1 Filter"},
3886 {"DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux"},
3888 {"DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux"},
3893 {"DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3894 {"DAC L2 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3895 {"DAC L2 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3896 {"DAC L2 Mux", "IF3 DAC", "IF3 DAC L"},
3897 {"DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL"},
3898 {"DAC L2 Mux", NULL, "DAC Mono Left Filter"},
3900 {"DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3901 {"DAC R2 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3902 {"DAC R2 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3903 {"DAC R2 Mux", "IF3 DAC", "IF3 DAC R"},
3904 {"DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR"},
3905 {"DAC R2 Mux", NULL, "DAC Mono Right Filter"},
3907 {"DAC L3 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3908 {"DAC L3 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3909 {"DAC L3 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3910 {"DAC L3 Mux", "IF3 DAC", "IF3 DAC L"},
3911 {"DAC L3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXL"},
3912 {"DAC L3 Mux", NULL, "DAC Stereo2 Filter"},
3914 {"DAC R3 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3915 {"DAC R3 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3916 {"DAC R3 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3917 {"DAC R3 Mux", "IF3 DAC", "IF3 DAC R"},
3918 {"DAC R3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXR"},
3919 {"DAC R3 Mux", NULL, "DAC Stereo2 Filter"},
3923 {"Stereo1 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3924 {"Stereo1 DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3928 {"Stereo1 DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3929 {"Stereo1 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3932 {"Stereo2 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3933 {"Stereo2 DAC MIXL", "DAC L3 Switch", "DAC L3 Mux"},
3936 {"Stereo2 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3937 {"Stereo2 DAC MIXR", "DAC R3 Switch", "DAC R3 Mux"},
3941 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3942 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3945 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3946 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3962 {"DAC L2 Source", "DAC2", "DAC L2 Mux"},
3965 {"DAC R2 Source", "DAC2", "DAC R2 Mux"},
4035 {"PDM L Mux", "Mono DAC", "Mono DAC MIXL"},
4036 {"PDM L Mux", "Stereo1 DAC", "Stereo1 DAC MIXL"},
4037 {"PDM L Mux", "Stereo2 DAC", "Stereo2 DAC MIXL"},
4038 {"PDM L Mux", NULL, "PDM Power"},
4039 {"PDM R Mux", "Mono DAC", "Mono DAC MIXR"},
4040 {"PDM R Mux", "Stereo1 DAC", "Stereo1 DAC MIXR"},
4041 {"PDM R Mux", "Stereo2 DAC", "Stereo2 DAC MIXR"},
4042 {"PDM R Mux", NULL, "PDM Power"},
4043 {"PDM L Playback", "Switch", "PDM L Mux"},
4044 {"PDM R Playback", "Switch", "PDM R Mux"},
4052 struct snd_soc_component *component = dai->component; in rt5665_set_tdm_slot()
4074 return -EINVAL; in rt5665_set_tdm_slot()
4093 return -EINVAL; in rt5665_set_tdm_slot()
4108 struct snd_soc_component *component = dai->component; in rt5665_hw_params()
4113 rt5665->lrck[dai->id] = params_rate(params); in rt5665_hw_params()
4114 pre_div = rl6231_get_clk_info(rt5665->sysclk, rt5665->lrck[dai->id]); in rt5665_hw_params()
4116 dev_warn(component->dev, "Force using PLL"); in rt5665_hw_params()
4118 rt5665->sysclk, rt5665->lrck[dai->id] * 512); in rt5665_hw_params()
4120 rt5665->lrck[dai->id] * 512, 0); in rt5665_hw_params()
4125 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); in rt5665_hw_params()
4126 return -EINVAL; in rt5665_hw_params()
4129 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", in rt5665_hw_params()
4130 rt5665->lrck[dai->id], pre_div, dai->id); in rt5665_hw_params()
4148 return -EINVAL; in rt5665_hw_params()
4151 switch (dai->id) { in rt5665_hw_params()
4179 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); in rt5665_hw_params()
4180 return -EINVAL; in rt5665_hw_params()
4186 switch (rt5665->lrck[dai->id]) { in rt5665_hw_params()
4204 if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) { in rt5665_hw_params()
4208 if (rt5665->master[RT5665_AIF3]) { in rt5665_hw_params()
4218 struct snd_soc_component *component = dai->component; in rt5665_set_dai_fmt()
4224 rt5665->master[dai->id] = 1; in rt5665_set_dai_fmt()
4228 rt5665->master[dai->id] = 0; in rt5665_set_dai_fmt()
4231 return -EINVAL; in rt5665_set_dai_fmt()
4241 return -EINVAL; in rt5665_set_dai_fmt()
4257 return -EINVAL; in rt5665_set_dai_fmt()
4260 switch (dai->id) { in rt5665_set_dai_fmt()
4279 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); in rt5665_set_dai_fmt()
4280 return -EINVAL; in rt5665_set_dai_fmt()
4291 if (freq == rt5665->sysclk && clk_id == rt5665->sysclk_src) in rt5665_set_component_sysclk()
4308 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); in rt5665_set_component_sysclk()
4309 return -EINVAL; in rt5665_set_component_sysclk()
4314 if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) { in rt5665_set_component_sysclk()
4318 if (rt5665->master[RT5665_AIF3]) { in rt5665_set_component_sysclk()
4323 rt5665->sysclk = freq; in rt5665_set_component_sysclk()
4324 rt5665->sysclk_src = clk_id; in rt5665_set_component_sysclk()
4326 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); in rt5665_set_component_sysclk()
4339 if (source == rt5665->pll_src && freq_in == rt5665->pll_in && in rt5665_set_component_pll()
4340 freq_out == rt5665->pll_out) in rt5665_set_component_pll()
4344 dev_dbg(component->dev, "PLL disabled\n"); in rt5665_set_component_pll()
4346 rt5665->pll_in = 0; in rt5665_set_component_pll()
4347 rt5665->pll_out = 0; in rt5665_set_component_pll()
4371 dev_err(component->dev, "Unknown PLL Source %d\n", source); in rt5665_set_component_pll()
4372 return -EINVAL; in rt5665_set_component_pll()
4377 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); in rt5665_set_component_pll()
4381 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", in rt5665_set_component_pll()
4391 rt5665->pll_in = freq_in; in rt5665_set_component_pll()
4392 rt5665->pll_out = freq_out; in rt5665_set_component_pll()
4393 rt5665->pll_src = source; in rt5665_set_component_pll()
4400 struct snd_soc_component *component = dai->component; in rt5665_set_bclk_ratio()
4403 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio); in rt5665_set_bclk_ratio()
4405 rt5665->bclk[dai->id] = ratio; in rt5665_set_bclk_ratio()
4408 switch (dai->id) { in rt5665_set_bclk_ratio()
4433 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC, in rt5665_set_bias_level()
4438 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1, in rt5665_set_bias_level()
4440 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1, in rt5665_set_bias_level()
4442 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC, in rt5665_set_bias_level()
4446 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1, in rt5665_set_bias_level()
4448 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1, in rt5665_set_bias_level()
4463 rt5665->component = component; in rt5665_probe()
4465 schedule_delayed_work(&rt5665->calibrate_work, msecs_to_jiffies(100)); in rt5665_probe()
4474 regmap_write(rt5665->regmap, RT5665_RESET, 0); in rt5665_remove()
4482 regcache_cache_only(rt5665->regmap, true); in rt5665_suspend()
4483 regcache_mark_dirty(rt5665->regmap); in rt5665_suspend()
4491 regcache_cache_only(rt5665->regmap, false); in rt5665_resume()
4492 regcache_sync(rt5665->regmap); in rt5665_resume()
4514 .name = "rt5665-aif1_1",
4533 .name = "rt5665-aif1_2",
4545 .name = "rt5665-aif2_1",
4564 .name = "rt5665-aif2_2",
4583 .name = "rt5665-aif3",
4645 rt5665->pdata.in1_diff = of_property_read_bool(dev->of_node, in rt5665_parse_dt()
4646 "realtek,in1-differential"); in rt5665_parse_dt()
4647 rt5665->pdata.in2_diff = of_property_read_bool(dev->of_node, in rt5665_parse_dt()
4648 "realtek,in2-differential"); in rt5665_parse_dt()
4649 rt5665->pdata.in3_diff = of_property_read_bool(dev->of_node, in rt5665_parse_dt()
4650 "realtek,in3-differential"); in rt5665_parse_dt()
4651 rt5665->pdata.in4_diff = of_property_read_bool(dev->of_node, in rt5665_parse_dt()
4652 "realtek,in4-differential"); in rt5665_parse_dt()
4654 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin", in rt5665_parse_dt()
4655 &rt5665->pdata.dmic1_data_pin); in rt5665_parse_dt()
4656 of_property_read_u32(dev->of_node, "realtek,dmic2-data-pin", in rt5665_parse_dt()
4657 &rt5665->pdata.dmic2_data_pin); in rt5665_parse_dt()
4658 of_property_read_u32(dev->of_node, "realtek,jd-src", in rt5665_parse_dt()
4659 &rt5665->pdata.jd_src); in rt5665_parse_dt()
4661 rt5665->pdata.ldo1_en = of_get_named_gpio(dev->of_node, in rt5665_parse_dt()
4662 "realtek,ldo1-en-gpios", 0); in rt5665_parse_dt()
4671 mutex_lock(&rt5665->calibrate_mutex); in rt5665_calibrate()
4673 regcache_cache_bypass(rt5665->regmap, true); in rt5665_calibrate()
4675 regmap_write(rt5665->regmap, RT5665_RESET, 0); in rt5665_calibrate()
4676 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602); in rt5665_calibrate()
4677 regmap_write(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, 0x0c26); in rt5665_calibrate()
4678 regmap_write(rt5665->regmap, RT5665_MONOMIX_IN_GAIN, 0x021f); in rt5665_calibrate()
4679 regmap_write(rt5665->regmap, RT5665_MONO_OUT, 0x480a); in rt5665_calibrate()
4680 regmap_write(rt5665->regmap, RT5665_PWR_MIXER, 0x083f); in rt5665_calibrate()
4681 regmap_write(rt5665->regmap, RT5665_PWR_DIG_1, 0x0180); in rt5665_calibrate()
4682 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_1, 0x4040); in rt5665_calibrate()
4683 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0000); in rt5665_calibrate()
4684 regmap_write(rt5665->regmap, RT5665_DIG_MISC, 0x0001); in rt5665_calibrate()
4685 regmap_write(rt5665->regmap, RT5665_MICBIAS_2, 0x0380); in rt5665_calibrate()
4686 regmap_write(rt5665->regmap, RT5665_GLB_CLK, 0x8000); in rt5665_calibrate()
4687 regmap_write(rt5665->regmap, RT5665_ADDA_CLK_1, 0x1000); in rt5665_calibrate()
4688 regmap_write(rt5665->regmap, RT5665_CHOP_DAC, 0x3030); in rt5665_calibrate()
4689 regmap_write(rt5665->regmap, RT5665_CALIB_ADC_CTRL, 0x3c05); in rt5665_calibrate()
4690 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xaa3e); in rt5665_calibrate()
4692 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xfe7e); in rt5665_calibrate()
4693 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_2, 0x0321); in rt5665_calibrate()
4695 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_1, 0xfc00); in rt5665_calibrate()
4698 regmap_read(rt5665->regmap, RT5665_HP_CALIB_STA_1, &value); in rt5665_calibrate()
4706 regmap_write(rt5665->regmap, RT5665_RESET, 0); in rt5665_calibrate()
4707 regcache_cache_bypass(rt5665->regmap, false); in rt5665_calibrate()
4714 regmap_write(rt5665->regmap, RT5665_MONO_AMP_CALIB_CTRL_1, 0x9e24); in rt5665_calibrate()
4717 regmap_read(rt5665->regmap, RT5665_MONO_AMP_CALIB_STA1, &value); in rt5665_calibrate()
4725 regmap_write(rt5665->regmap, RT5665_RESET, 0); in rt5665_calibrate()
4726 regcache_cache_bypass(rt5665->regmap, false); in rt5665_calibrate()
4733 regmap_write(rt5665->regmap, RT5665_RESET, 0); in rt5665_calibrate()
4734 regcache_cache_bypass(rt5665->regmap, false); in rt5665_calibrate()
4736 regcache_mark_dirty(rt5665->regmap); in rt5665_calibrate()
4737 regcache_sync(rt5665->regmap); in rt5665_calibrate()
4739 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602); in rt5665_calibrate()
4740 regmap_write(rt5665->regmap, RT5665_ASRC_8, 0x0120); in rt5665_calibrate()
4743 rt5665->calibration_done = true; in rt5665_calibrate()
4744 mutex_unlock(&rt5665->calibrate_mutex); in rt5665_calibrate()
4752 while (!rt5665->component->card->instantiated) { in rt5665_calibrate_handler()
4763 struct rt5665_platform_data *pdata = dev_get_platdata(&i2c->dev); in rt5665_i2c_probe()
4768 rt5665 = devm_kzalloc(&i2c->dev, sizeof(struct rt5665_priv), in rt5665_i2c_probe()
4772 return -ENOMEM; in rt5665_i2c_probe()
4777 rt5665->pdata = *pdata; in rt5665_i2c_probe()
4779 rt5665_parse_dt(rt5665, &i2c->dev); in rt5665_i2c_probe()
4781 for (i = 0; i < ARRAY_SIZE(rt5665->supplies); i++) in rt5665_i2c_probe()
4782 rt5665->supplies[i].supply = rt5665_supply_names[i]; in rt5665_i2c_probe()
4784 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5665->supplies), in rt5665_i2c_probe()
4785 rt5665->supplies); in rt5665_i2c_probe()
4787 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); in rt5665_i2c_probe()
4791 ret = regulator_bulk_enable(ARRAY_SIZE(rt5665->supplies), in rt5665_i2c_probe()
4792 rt5665->supplies); in rt5665_i2c_probe()
4794 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); in rt5665_i2c_probe()
4798 if (gpio_is_valid(rt5665->pdata.ldo1_en)) { in rt5665_i2c_probe()
4799 if (devm_gpio_request_one(&i2c->dev, rt5665->pdata.ldo1_en, in rt5665_i2c_probe()
4801 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n"); in rt5665_i2c_probe()
4807 rt5665->regmap = devm_regmap_init_i2c(i2c, &rt5665_regmap); in rt5665_i2c_probe()
4808 if (IS_ERR(rt5665->regmap)) { in rt5665_i2c_probe()
4809 ret = PTR_ERR(rt5665->regmap); in rt5665_i2c_probe()
4810 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", in rt5665_i2c_probe()
4815 regmap_read(rt5665->regmap, RT5665_DEVICE_ID, &val); in rt5665_i2c_probe()
4817 dev_err(&i2c->dev, in rt5665_i2c_probe()
4819 return -ENODEV; in rt5665_i2c_probe()
4822 regmap_read(rt5665->regmap, RT5665_RESET, &val); in rt5665_i2c_probe()
4825 rt5665->id = CODEC_5666; in rt5665_i2c_probe()
4829 rt5665->id = CODEC_5665; in rt5665_i2c_probe()
4833 regmap_write(rt5665->regmap, RT5665_RESET, 0); in rt5665_i2c_probe()
4836 if (rt5665->pdata.in1_diff) in rt5665_i2c_probe()
4837 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2, in rt5665_i2c_probe()
4839 if (rt5665->pdata.in2_diff) in rt5665_i2c_probe()
4840 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2, in rt5665_i2c_probe()
4842 if (rt5665->pdata.in3_diff) in rt5665_i2c_probe()
4843 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4, in rt5665_i2c_probe()
4845 if (rt5665->pdata.in4_diff) in rt5665_i2c_probe()
4846 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4, in rt5665_i2c_probe()
4850 if (rt5665->pdata.dmic1_data_pin != RT5665_DMIC1_NULL || in rt5665_i2c_probe()
4851 rt5665->pdata.dmic2_data_pin != RT5665_DMIC2_NULL) { in rt5665_i2c_probe()
4852 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2, in rt5665_i2c_probe()
4854 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1, in rt5665_i2c_probe()
4856 switch (rt5665->pdata.dmic1_data_pin) { in rt5665_i2c_probe()
4858 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1, in rt5665_i2c_probe()
4863 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1, in rt5665_i2c_probe()
4865 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1, in rt5665_i2c_probe()
4870 dev_dbg(&i2c->dev, "no DMIC1\n"); in rt5665_i2c_probe()
4874 switch (rt5665->pdata.dmic2_data_pin) { in rt5665_i2c_probe()
4876 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1, in rt5665_i2c_probe()
4881 regmap_update_bits(rt5665->regmap, in rt5665_i2c_probe()
4885 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1, in rt5665_i2c_probe()
4890 dev_dbg(&i2c->dev, "no DMIC2\n"); in rt5665_i2c_probe()
4896 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0002); in rt5665_i2c_probe()
4897 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1, in rt5665_i2c_probe()
4900 regmap_update_bits(rt5665->regmap, RT5665_STO1_DAC_SIL_DET, in rt5665_i2c_probe()
4903 regmap_update_bits(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, in rt5665_i2c_probe()
4907 if (rt5665->id == CODEC_5666) { in rt5665_i2c_probe()
4908 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2, in rt5665_i2c_probe()
4910 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_3, in rt5665_i2c_probe()
4915 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1, in rt5665_i2c_probe()
4919 INIT_DELAYED_WORK(&rt5665->jack_detect_work, in rt5665_i2c_probe()
4921 INIT_DELAYED_WORK(&rt5665->calibrate_work, in rt5665_i2c_probe()
4923 INIT_DELAYED_WORK(&rt5665->jd_check_work, in rt5665_i2c_probe()
4926 mutex_init(&rt5665->calibrate_mutex); in rt5665_i2c_probe()
4928 if (i2c->irq) { in rt5665_i2c_probe()
4929 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, in rt5665_i2c_probe()
4933 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret); in rt5665_i2c_probe()
4937 return devm_snd_soc_register_component(&i2c->dev, in rt5665_i2c_probe()
4946 regmap_write(rt5665->regmap, RT5665_RESET, 0); in rt5665_i2c_shutdown()