Lines Matching +full:adc +full:- +full:mux
1 // SPDX-License-Identifier: GPL-2.0-only
3 * rt5659.c -- RT5659/RT5658 ALSA SoC audio codec driver
26 #include <sound/soc-dapm.h>
1137 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2325, 75, 0);
1138 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
1139 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
1140 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
1141 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
1143 static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
1175 SOC_DAPM_ENUM("IF1 01 ADC Swap Source", rt5659_if1_01_adc_enum);
1190 SOC_DAPM_ENUM("IF2 ADC Swap Source", rt5659_if2_adc_enum);
1196 SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5659_if3_adc_enum);
1250 * rt5659_headset_detect - Detect headset.
1297 rt5659->jack_type = SND_JACK_HEADSET; in rt5659_headset_detect()
1302 rt5659->jack_type = SND_JACK_HEADPHONE; in rt5659_headset_detect()
1310 if (rt5659->jack_type == SND_JACK_HEADSET) in rt5659_headset_detect()
1312 rt5659->jack_type = 0; in rt5659_headset_detect()
1315 dev_dbg(component->dev, "jack_type = %d\n", rt5659->jack_type); in rt5659_headset_detect()
1316 return rt5659->jack_type; in rt5659_headset_detect()
1335 &rt5659->jack_detect_work, msecs_to_jiffies(250)); in rt5659_irq()
1345 rt5659->hs_jack = hs_jack; in rt5659_set_jack_detect()
1359 if (!rt5659->component) in rt5659_jack_detect_work()
1362 val = snd_soc_component_read(rt5659->component, RT5659_INT_ST_1) & 0x0080; in rt5659_jack_detect_work()
1365 if (rt5659->jack_type == 0) { in rt5659_jack_detect_work()
1367 report = rt5659_headset_detect(rt5659->component, 1); in rt5659_jack_detect_work()
1371 btn_type = rt5659_button_detect(rt5659->component); in rt5659_jack_detect_work()
1404 dev_err(rt5659->component->dev, in rt5659_jack_detect_work()
1412 report = rt5659->jack_type; in rt5659_jack_detect_work()
1416 report = rt5659_headset_detect(rt5659->component, 0); in rt5659_jack_detect_work()
1419 snd_soc_jack_report(rt5659->hs_jack, report, SND_JACK_HEADSET | in rt5659_jack_detect_work()
1431 if (!rt5659->hs_jack) in rt5659_jack_detect_intel_hd_header()
1435 regmap_read(rt5659->regmap, RT5659_GPIO_STA, &value); in rt5659_jack_detect_intel_hd_header()
1438 if (hp_flag != rt5659->hda_hp_plugged) { in rt5659_jack_detect_intel_hd_header()
1439 rt5659->hda_hp_plugged = hp_flag; in rt5659_jack_detect_intel_hd_header()
1442 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1, in rt5659_jack_detect_intel_hd_header()
1444 rt5659->jack_type |= SND_JACK_HEADPHONE; in rt5659_jack_detect_intel_hd_header()
1446 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1, in rt5659_jack_detect_intel_hd_header()
1448 rt5659->jack_type = rt5659->jack_type & in rt5659_jack_detect_intel_hd_header()
1452 snd_soc_jack_report(rt5659->hs_jack, rt5659->jack_type, in rt5659_jack_detect_intel_hd_header()
1457 regmap_read(rt5659->regmap, RT5659_4BTN_IL_CMD_1, &value); in rt5659_jack_detect_intel_hd_header()
1458 regmap_write(rt5659->regmap, RT5659_4BTN_IL_CMD_1, value); in rt5659_jack_detect_intel_hd_header()
1461 if (mic_flag != rt5659->hda_mic_plugged) { in rt5659_jack_detect_intel_hd_header()
1462 rt5659->hda_mic_plugged = mic_flag; in rt5659_jack_detect_intel_hd_header()
1464 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2, in rt5659_jack_detect_intel_hd_header()
1466 rt5659->jack_type |= SND_JACK_MICROPHONE; in rt5659_jack_detect_intel_hd_header()
1468 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2, in rt5659_jack_detect_intel_hd_header()
1470 rt5659->jack_type = rt5659->jack_type in rt5659_jack_detect_intel_hd_header()
1474 snd_soc_jack_report(rt5659->hs_jack, rt5659->jack_type, in rt5659_jack_detect_intel_hd_header()
1522 /* ADC Digital Volume Control */
1523 SOC_DOUBLE("STO1 ADC Capture Switch", RT5659_STO1_ADC_DIG_VOL,
1525 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5659_STO1_ADC_DIG_VOL,
1527 SOC_DOUBLE("Mono ADC Capture Switch", RT5659_MONO_ADC_DIG_VOL,
1529 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5659_MONO_ADC_DIG_VOL,
1531 SOC_DOUBLE("STO2 ADC Capture Switch", RT5659_STO2_ADC_DIG_VOL,
1533 SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5659_STO2_ADC_DIG_VOL,
1536 /* ADC Boost Volume Control */
1537 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5659_STO1_BOOST,
1541 SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5659_MONO_BOOST,
1545 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5659_STO2_BOOST,
1556 * set_dmic_clk - Set parameter of dmic.
1568 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in set_dmic_clk()
1572 pd = rl6231_get_pre_div(rt5659->regmap, in set_dmic_clk()
1574 idx = rl6231_calc_dmic_clk(rt5659->sysclk / pd); in set_dmic_clk()
1577 dev_err(component->dev, "Failed to set DMIC clock\n"); in set_dmic_clk()
1588 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in set_adc1_clk()
1614 snd_soc_dapm_to_component(w->dapm); in set_adc2_clk()
1639 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5659_charge_pump_event()
1660 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in is_sys_clk_from_pll()
1674 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in is_using_asrc()
1676 switch (w->shift) { in is_using_asrc()
1750 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5659_AD_DA_MIXER,
1757 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5659_AD_DA_MIXER,
1969 /*MX-1B [6:4], MX-1B [2:0]*/
1971 "IF1 DAC2", "IF2 DAC", "IF3 DAC", "Mono ADC MIX"
1990 /* MX-26 [13] */
1992 "DAC MIX", "ADC"
2002 /* STO1 ADC Source */
2003 /* MX-26 [12] */
2013 SOC_DAPM_ENUM("Stereo1 ADC Source", rt5659_sto1_adc_enum);
2016 /* MX-26 [11] */
2029 /* MX-26 [8] */
2042 /* MONO ADC L2 Source */
2043 /* MX-27 [12] */
2053 SOC_DAPM_ENUM("Mono ADC L2 Source", rt5659_mono_adc_l2_enum);
2056 /* MONO ADC L1 Source */
2057 /* MX-27 [11] */
2059 "Mono DAC MIXL", "ADC"
2067 SOC_DAPM_ENUM("Mono ADC L1 Source", rt5659_mono_adc_l1_enum);
2069 /* MONO ADC L Source, MONO ADC R Source*/
2070 /* MX-27 [10:9], MX-27 [2:1] */
2080 SOC_DAPM_ENUM("Mono ADC L Source", rt5659_mono_adc_l_enum);
2087 SOC_DAPM_ENUM("Mono ADC R Source", rt5659_mono_adcr_enum);
2090 /* MX-27 [8] */
2102 /* MONO ADC R2 Source */
2103 /* MX-27 [4] */
2113 SOC_DAPM_ENUM("Mono ADC R2 Source", rt5659_mono_adc_r2_enum);
2115 /* MONO ADC R1 Source */
2116 /* MX-27 [3] */
2118 "Mono DAC MIXR", "ADC"
2126 SOC_DAPM_ENUM("Mono ADC R1 Source", rt5659_mono_adc_r1_enum);
2129 /* MX-27 [0] */
2143 /* MX-29 [11:10], MX-29 [9:8]*/
2163 /* MX-2C [6], MX-2C [4]*/
2183 /* MX-2D [3], MX-2D [2]*/
2203 /* MX-2D [1], MX-2D [0]*/
2222 /* Interface2 ADC Data Input*/
2223 /* MX-2F [13:12] */
2233 SOC_DAPM_ENUM("IF2 ADC IN Source", rt5659_if2_adc_in_enum);
2235 /* Interface3 ADC Data Input*/
2236 /* MX-2F [1:0] */
2246 SOC_DAPM_ENUM("IF3 ADC IN Source", rt5659_if3_adc_in_enum);
2249 /* MX-31 [15] [13] */
2269 /* MX-36 [1:0] */
2282 /* MX-78[4:0] */
2347 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5659_spk_event()
2379 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5659_mono_event()
2401 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5659_hp_event()
2464 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5659_ASRC_1,
2466 SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5659_ASRC_1,
2468 SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5659_ASRC_1,
2556 /* ADC Mux */
2557 SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2559 SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2561 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2563 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2565 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2567 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2569 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2571 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2573 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2575 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2577 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2579 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2581 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2583 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2585 SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
2587 SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
2589 /* ADC Mixer */
2590 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5659_PWR_DIG_2,
2592 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5659_PWR_DIG_2,
2594 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM,
2597 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM,
2600 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5659_PWR_DIG_2,
2602 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5659_MONO_ADC_DIG_VOL,
2605 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5659_PWR_DIG_2,
2607 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5659_MONO_ADC_DIG_VOL,
2611 /* ADC PGA */
2619 SND_SOC_DAPM_PGA("Stereo2 ADC LR", SND_SOC_NOPM, 0, 0, NULL, 0),
2621 SND_SOC_DAPM_PGA("Stereo1 ADC Volume L", RT5659_STO1_ADC_DIG_VOL,
2623 SND_SOC_DAPM_PGA("Stereo1 ADC Volume R", RT5659_STO1_ADC_DIG_VOL,
2635 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2636 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2637 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2643 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2651 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2652 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2653 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2658 SND_SOC_DAPM_MUX("TDM Data Mux", SND_SOC_NOPM, 0, 0,
2660 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 0, 0,
2662 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2664 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2666 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2668 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2670 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2672 SND_SOC_DAPM_MUX("IF2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2674 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2676 SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2678 SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2696 /* DAC channel Mux */
2697 SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_l1_mux),
2698 SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_r1_mux),
2699 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_l2_mux),
2700 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_r2_mux),
2817 SND_SOC_DAPM_MUX("PDM L Mux", RT5659_PDM_OUT_CTRL,
2819 SND_SOC_DAPM_MUX("PDM R Mux", RT5659_PDM_OUT_CTRL,
2823 SND_SOC_DAPM_MUX("SPDIF Mux", SND_SOC_NOPM, 0, 0, &rt5659_spdif_mux),
2843 { "ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll },
2844 { "ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll },
2845 { "ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll },
2846 { "ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll },
2852 { "ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc },
2853 { "ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc },
2854 { "ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc },
2937 { "Stereo1 DMIC L Mux", "DMIC1", "DMIC L1" },
2938 { "Stereo1 DMIC L Mux", "DMIC2", "DMIC L2" },
2940 { "Stereo1 DMIC R Mux", "DMIC1", "DMIC R1" },
2941 { "Stereo1 DMIC R Mux", "DMIC2", "DMIC R2" },
2943 { "Mono DMIC L Mux", "DMIC1 L", "DMIC L1" },
2944 { "Mono DMIC L Mux", "DMIC2 L", "DMIC L2" },
2946 { "Mono DMIC R Mux", "DMIC1 R", "DMIC R1" },
2947 { "Mono DMIC R Mux", "DMIC2 R", "DMIC R2" },
2949 { "Stereo1 ADC L Mux", "ADC1", "ADC1 L" },
2950 { "Stereo1 ADC L Mux", "ADC2", "ADC2 L" },
2951 { "Stereo1 ADC R Mux", "ADC1", "ADC1 R" },
2952 { "Stereo1 ADC R Mux", "ADC2", "ADC2 R" },
2954 { "Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux" },
2955 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
2956 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux" },
2957 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
2959 { "Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux" },
2960 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
2961 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux" },
2962 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
2964 { "Mono ADC L Mux", "ADC1 L", "ADC1 L" },
2965 { "Mono ADC L Mux", "ADC1 R", "ADC1 R" },
2966 { "Mono ADC L Mux", "ADC2 L", "ADC2 L" },
2967 { "Mono ADC L Mux", "ADC2 R", "ADC2 R" },
2969 { "Mono ADC R Mux", "ADC1 L", "ADC1 L" },
2970 { "Mono ADC R Mux", "ADC1 R", "ADC1 R" },
2971 { "Mono ADC R Mux", "ADC2 L", "ADC2 L" },
2972 { "Mono ADC R Mux", "ADC2 R", "ADC2 R" },
2974 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
2975 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2976 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2977 { "Mono ADC L1 Mux", "ADC", "Mono ADC L Mux" },
2979 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2980 { "Mono ADC R1 Mux", "ADC", "Mono ADC R Mux" },
2981 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
2982 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2984 { "Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
2985 { "Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
2986 { "Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter" },
2988 { "Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
2989 { "Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
2990 { "Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter" },
2992 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
2993 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
2994 { "Mono ADC MIXL", NULL, "ADC Mono Left Filter" },
2996 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
2997 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
2998 { "Mono ADC MIXR", NULL, "ADC Mono Right Filter" },
3000 { "Stereo1 ADC Volume L", NULL, "Stereo1 ADC MIXL" },
3001 { "Stereo1 ADC Volume R", NULL, "Stereo1 ADC MIXR" },
3003 { "IF_ADC1", NULL, "Stereo1 ADC Volume L" },
3004 { "IF_ADC1", NULL, "Stereo1 ADC Volume R" },
3005 { "IF_ADC2", NULL, "Mono ADC MIXL" },
3006 { "IF_ADC2", NULL, "Mono ADC MIXR" },
3013 { "TDM Data Mux", "AD1:AD2:DAC:NUL", "TDM AD1:AD2:DAC" },
3014 { "TDM Data Mux", "AD1:AD2:NUL:DAC", "TDM AD1:AD2:DAC" },
3015 { "TDM Data Mux", "AD1:DAC:AD2:NUL", "TDM AD1:AD2:DAC" },
3016 { "TDM Data Mux", "AD1:DAC:NUL:AD2", "TDM AD1:AD2:DAC" },
3017 { "TDM Data Mux", "AD1:NUL:DAC:AD2", "TDM AD1:AD2:DAC" },
3018 { "TDM Data Mux", "AD1:NUL:AD2:DAC", "TDM AD1:AD2:DAC" },
3019 { "TDM Data Mux", "AD2:AD1:DAC:NUL", "TDM AD1:AD2:DAC" },
3020 { "TDM Data Mux", "AD2:AD1:NUL:DAC", "TDM AD1:AD2:DAC" },
3021 { "TDM Data Mux", "AD2:DAC:AD1:NUL", "TDM AD1:AD2:DAC" },
3022 { "TDM Data Mux", "AD2:DAC:NUL:AD1", "TDM AD1:AD2:DAC" },
3023 { "TDM Data Mux", "AD2:NUL:DAC:AD1", "TDM AD1:AD2:DAC" },
3024 { "TDM Data Mux", "AD1:NUL:AD1:DAC", "TDM AD1:AD2:DAC" },
3025 { "TDM Data Mux", "DAC:AD1:AD2:NUL", "TDM AD1:AD2:DAC" },
3026 { "TDM Data Mux", "DAC:AD1:NUL:AD2", "TDM AD1:AD2:DAC" },
3027 { "TDM Data Mux", "DAC:AD2:AD1:NUL", "TDM AD1:AD2:DAC" },
3028 { "TDM Data Mux", "DAC:AD2:NUL:AD1", "TDM AD1:AD2:DAC" },
3029 { "TDM Data Mux", "DAC:NUL:DAC:AD2", "TDM AD2:DAC" },
3030 { "TDM Data Mux", "DAC:NUL:AD2:DAC", "TDM AD2:DAC" },
3031 { "TDM Data Mux", "NUL:AD1:AD2:DAC", "TDM AD1:AD2:DAC" },
3032 { "TDM Data Mux", "NUL:AD1:DAC:AD2", "TDM AD1:AD2:DAC" },
3033 { "TDM Data Mux", "NUL:AD2:AD1:DAC", "TDM AD1:AD2:DAC" },
3034 { "TDM Data Mux", "NUL:AD2:DAC:AD1", "TDM AD1:AD2:DAC" },
3035 { "TDM Data Mux", "NUL:DAC:DAC:AD2", "TDM AD2:DAC" },
3036 { "TDM Data Mux", "NUL:DAC:AD2:DAC", "TDM AD2:DAC" },
3037 { "IF1 01 ADC Swap Mux", "L/R", "TDM Data Mux" },
3038 { "IF1 01 ADC Swap Mux", "R/L", "TDM Data Mux" },
3039 { "IF1 01 ADC Swap Mux", "L/L", "TDM Data Mux" },
3040 { "IF1 01 ADC Swap Mux", "R/R", "TDM Data Mux" },
3041 { "IF1 23 ADC Swap Mux", "L/R", "TDM Data Mux" },
3042 { "IF1 23 ADC Swap Mux", "R/L", "TDM Data Mux" },
3043 { "IF1 23 ADC Swap Mux", "L/L", "TDM Data Mux" },
3044 { "IF1 23 ADC Swap Mux", "R/R", "TDM Data Mux" },
3045 { "IF1 45 ADC Swap Mux", "L/R", "TDM Data Mux" },
3046 { "IF1 45 ADC Swap Mux", "R/L", "TDM Data Mux" },
3047 { "IF1 45 ADC Swap Mux", "L/L", "TDM Data Mux" },
3048 { "IF1 45 ADC Swap Mux", "R/R", "TDM Data Mux" },
3049 { "IF1 67 ADC Swap Mux", "L/R", "TDM Data Mux" },
3050 { "IF1 67 ADC Swap Mux", "R/L", "TDM Data Mux" },
3051 { "IF1 67 ADC Swap Mux", "L/L", "TDM Data Mux" },
3052 { "IF1 67 ADC Swap Mux", "R/R", "TDM Data Mux" },
3053 { "IF1 ADC", NULL, "IF1 01 ADC Swap Mux" },
3054 { "IF1 ADC", NULL, "IF1 23 ADC Swap Mux" },
3055 { "IF1 ADC", NULL, "IF1 45 ADC Swap Mux" },
3056 { "IF1 ADC", NULL, "IF1 67 ADC Swap Mux" },
3057 { "IF1 ADC", NULL, "I2S1" },
3059 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
3060 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
3061 { "IF2 ADC Mux", "IF_ADC3", "IF_ADC3" },
3062 { "IF2 ADC Mux", "DAC_REF", "DAC_REF" },
3063 { "IF2 ADC", NULL, "IF2 ADC Mux"},
3064 { "IF2 ADC", NULL, "I2S2" },
3066 { "IF3 ADC Mux", "IF_ADC1", "IF_ADC1" },
3067 { "IF3 ADC Mux", "IF_ADC2", "IF_ADC2" },
3068 { "IF3 ADC Mux", "Stereo2_ADC_L/R", "Stereo2 ADC LR" },
3069 { "IF3 ADC Mux", "DAC_REF", "DAC_REF" },
3070 { "IF3 ADC", NULL, "IF3 ADC Mux"},
3071 { "IF3 ADC", NULL, "I2S3" },
3073 { "AIF1TX", NULL, "IF1 ADC" },
3074 { "IF2 ADC Swap Mux", "L/R", "IF2 ADC" },
3075 { "IF2 ADC Swap Mux", "R/L", "IF2 ADC" },
3076 { "IF2 ADC Swap Mux", "L/L", "IF2 ADC" },
3077 { "IF2 ADC Swap Mux", "R/R", "IF2 ADC" },
3078 { "AIF2TX", NULL, "IF2 ADC Swap Mux" },
3079 { "IF3 ADC Swap Mux", "L/R", "IF3 ADC" },
3080 { "IF3 ADC Swap Mux", "R/L", "IF3 ADC" },
3081 { "IF3 ADC Swap Mux", "L/L", "IF3 ADC" },
3082 { "IF3 ADC Swap Mux", "R/R", "IF3 ADC" },
3083 { "AIF3TX", NULL, "IF3 ADC Swap Mux" },
3087 { "IF2 DAC Swap Mux", "L/R", "AIF2RX" },
3088 { "IF2 DAC Swap Mux", "R/L", "AIF2RX" },
3089 { "IF2 DAC Swap Mux", "L/L", "AIF2RX" },
3090 { "IF2 DAC Swap Mux", "R/R", "AIF2RX" },
3091 { "IF2 DAC", NULL, "IF2 DAC Swap Mux" },
3092 { "IF3 DAC Swap Mux", "L/R", "AIF3RX" },
3093 { "IF3 DAC Swap Mux", "R/L", "AIF3RX" },
3094 { "IF3 DAC Swap Mux", "L/L", "AIF3RX" },
3095 { "IF3 DAC Swap Mux", "R/R", "AIF3RX" },
3096 { "IF3 DAC", NULL, "IF3 DAC Swap Mux" },
3112 { "DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L" },
3113 { "DAC L1 Mux", "IF2 DAC", "IF2 DAC L" },
3114 { "DAC L1 Mux", "IF3 DAC", "IF3 DAC L" },
3115 { "DAC L1 Mux", NULL, "DAC Stereo1 Filter" },
3117 { "DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R" },
3118 { "DAC R1 Mux", "IF2 DAC", "IF2 DAC R" },
3119 { "DAC R1 Mux", "IF3 DAC", "IF3 DAC R" },
3120 { "DAC R1 Mux", NULL, "DAC Stereo1 Filter" },
3122 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC Volume L" },
3123 { "DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux" },
3124 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC Volume R" },
3125 { "DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux" },
3130 { "DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L" },
3131 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
3132 { "DAC L2 Mux", "IF3 DAC", "IF3 DAC L" },
3133 { "DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL" },
3134 { "DAC L2 Mux", NULL, "DAC Mono Left Filter" },
3136 { "DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R" },
3137 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
3138 { "DAC R2 Mux", "IF3 DAC", "IF3 DAC R" },
3139 { "DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR" },
3140 { "DAC R2 Mux", NULL, "DAC Mono Right Filter" },
3144 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Mux" },
3145 { "Stereo DAC MIXL", "DAC R2 Switch", "DAC R2 Mux" },
3149 { "Stereo DAC MIXR", "DAC L2 Switch", "DAC L2 Mux" },
3150 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Mux" },
3154 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux" },
3155 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux" },
3158 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux" },
3159 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux" },
3258 { "PDM L Mux", "Mono DAC", "Mono DAC MIXL" },
3259 { "PDM L Mux", "Stereo DAC", "Stereo DAC MIXL" },
3260 { "PDM L Mux", NULL, "PDM Power" },
3261 { "PDM R Mux", "Mono DAC", "Mono DAC MIXR" },
3262 { "PDM R Mux", "Stereo DAC", "Stereo DAC MIXR" },
3263 { "PDM R Mux", NULL, "PDM Power" },
3264 { "PDM L Playback", "Switch", "PDM L Mux" },
3265 { "PDM R Playback", "Switch", "PDM R Mux" },
3269 { "SPDIF Mux", "IF3_DAC", "IF3 DAC" },
3270 { "SPDIF Mux", "IF2_DAC", "IF2 DAC" },
3271 { "SPDIF Mux", "IF1_DAC2", "IF1 DAC2" },
3272 { "SPDIF Mux", "IF1_DAC1", "IF1 DAC1" },
3273 { "SPDIF", NULL, "SPDIF Mux" },
3279 struct snd_soc_component *component = dai->component; in rt5659_hw_params()
3284 rt5659->lrck[dai->id] = params_rate(params); in rt5659_hw_params()
3285 pre_div = rl6231_get_clk_info(rt5659->sysclk, rt5659->lrck[dai->id]); in rt5659_hw_params()
3287 dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n", in rt5659_hw_params()
3288 rt5659->lrck[dai->id], dai->id); in rt5659_hw_params()
3289 return -EINVAL; in rt5659_hw_params()
3293 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); in rt5659_hw_params()
3294 return -EINVAL; in rt5659_hw_params()
3297 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", in rt5659_hw_params()
3298 rt5659->lrck[dai->id], pre_div, dai->id); in rt5659_hw_params()
3313 return -EINVAL; in rt5659_hw_params()
3316 switch (dai->id) { in rt5659_hw_params()
3336 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); in rt5659_hw_params()
3337 return -EINVAL; in rt5659_hw_params()
3342 switch (rt5659->lrck[dai->id]) { in rt5659_hw_params()
3362 struct snd_soc_component *component = dai->component; in rt5659_set_dai_fmt()
3368 rt5659->master[dai->id] = 1; in rt5659_set_dai_fmt()
3372 rt5659->master[dai->id] = 0; in rt5659_set_dai_fmt()
3375 return -EINVAL; in rt5659_set_dai_fmt()
3385 return -EINVAL; in rt5659_set_dai_fmt()
3401 return -EINVAL; in rt5659_set_dai_fmt()
3404 switch (dai->id) { in rt5659_set_dai_fmt()
3421 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); in rt5659_set_dai_fmt()
3422 return -EINVAL; in rt5659_set_dai_fmt()
3434 if (freq == rt5659->sysclk && clk_id == rt5659->sysclk_src) in rt5659_set_component_sysclk()
3439 ret = clk_set_rate(rt5659->mclk, freq); in rt5659_set_component_sysclk()
3452 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); in rt5659_set_component_sysclk()
3453 return -EINVAL; in rt5659_set_component_sysclk()
3457 rt5659->sysclk = freq; in rt5659_set_component_sysclk()
3458 rt5659->sysclk_src = clk_id; in rt5659_set_component_sysclk()
3460 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", in rt5659_set_component_sysclk()
3474 if (source == rt5659->pll_src && freq_in == rt5659->pll_in && in rt5659_set_component_pll()
3475 freq_out == rt5659->pll_out) in rt5659_set_component_pll()
3479 dev_dbg(component->dev, "PLL disabled\n"); in rt5659_set_component_pll()
3481 rt5659->pll_in = 0; in rt5659_set_component_pll()
3482 rt5659->pll_out = 0; in rt5659_set_component_pll()
3506 dev_err(component->dev, "Unknown PLL source %d\n", source); in rt5659_set_component_pll()
3507 return -EINVAL; in rt5659_set_component_pll()
3512 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); in rt5659_set_component_pll()
3516 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", in rt5659_set_component_pll()
3526 rt5659->pll_in = freq_in; in rt5659_set_component_pll()
3527 rt5659->pll_out = freq_out; in rt5659_set_component_pll()
3528 rt5659->pll_src = source; in rt5659_set_component_pll()
3536 struct snd_soc_component *component = dai->component; in rt5659_set_tdm_slot()
3558 return -EINVAL; in rt5659_set_tdm_slot()
3577 return -EINVAL; in rt5659_set_tdm_slot()
3587 struct snd_soc_component *component = dai->component; in rt5659_set_bclk_ratio()
3590 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio); in rt5659_set_bclk_ratio()
3592 rt5659->bclk[dai->id] = ratio; in rt5659_set_bclk_ratio()
3595 switch (dai->id) { in rt5659_set_bclk_ratio()
3621 regmap_update_bits(rt5659->regmap, RT5659_DIG_MISC, in rt5659_set_bias_level()
3623 regmap_update_bits(rt5659->regmap, RT5659_PWR_DIG_1, in rt5659_set_bias_level()
3625 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1, in rt5659_set_bias_level()
3629 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1, in rt5659_set_bias_level()
3635 if (dapm->bias_level == SND_SOC_BIAS_OFF) { in rt5659_set_bias_level()
3636 ret = clk_prepare_enable(rt5659->mclk); in rt5659_set_bias_level()
3638 dev_err(component->dev, in rt5659_set_bias_level()
3646 regmap_update_bits(rt5659->regmap, RT5659_PWR_DIG_1, in rt5659_set_bias_level()
3648 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1, in rt5659_set_bias_level()
3652 regmap_update_bits(rt5659->regmap, RT5659_DIG_MISC, in rt5659_set_bias_level()
3654 clk_disable_unprepare(rt5659->mclk); in rt5659_set_bias_level()
3670 rt5659->component = component; in rt5659_probe()
3672 switch (rt5659->pdata.jd_src) { in rt5659_probe()
3690 regmap_write(rt5659->regmap, RT5659_RESET, 0); in rt5659_remove()
3698 regcache_cache_only(rt5659->regmap, true); in rt5659_suspend()
3699 regcache_mark_dirty(rt5659->regmap); in rt5659_suspend()
3707 regcache_cache_only(rt5659->regmap, false); in rt5659_resume()
3708 regcache_sync(rt5659->regmap); in rt5659_resume()
3730 .name = "rt5659-aif1",
3749 .name = "rt5659-aif2",
3768 .name = "rt5659-aif3",
3828 rt5659->pdata.in1_diff = device_property_read_bool(dev, in rt5659_parse_dt()
3829 "realtek,in1-differential"); in rt5659_parse_dt()
3830 rt5659->pdata.in3_diff = device_property_read_bool(dev, in rt5659_parse_dt()
3831 "realtek,in3-differential"); in rt5659_parse_dt()
3832 rt5659->pdata.in4_diff = device_property_read_bool(dev, in rt5659_parse_dt()
3833 "realtek,in4-differential"); in rt5659_parse_dt()
3836 device_property_read_u32(dev, "realtek,dmic1-data-pin", in rt5659_parse_dt()
3837 &rt5659->pdata.dmic1_data_pin); in rt5659_parse_dt()
3838 device_property_read_u32(dev, "realtek,dmic2-data-pin", in rt5659_parse_dt()
3839 &rt5659->pdata.dmic2_data_pin); in rt5659_parse_dt()
3840 device_property_read_u32(dev, "realtek,jd-src", in rt5659_parse_dt()
3841 &rt5659->pdata.jd_src); in rt5659_parse_dt()
3852 regmap_write(rt5659->regmap, RT5659_BIAS_CUR_CTRL_8, 0xa502); in rt5659_calibrate()
3853 regmap_write(rt5659->regmap, RT5659_CHOP_DAC, 0x3030); in rt5659_calibrate()
3855 regmap_write(rt5659->regmap, RT5659_PRE_DIV_1, 0xef00); in rt5659_calibrate()
3856 regmap_write(rt5659->regmap, RT5659_PRE_DIV_2, 0xeffc); in rt5659_calibrate()
3857 regmap_write(rt5659->regmap, RT5659_MICBIAS_2, 0x0280); in rt5659_calibrate()
3858 regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x0001); in rt5659_calibrate()
3859 regmap_write(rt5659->regmap, RT5659_GLB_CLK, 0x8000); in rt5659_calibrate()
3861 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xaa7e); in rt5659_calibrate()
3863 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xfe7e); in rt5659_calibrate()
3865 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0004); in rt5659_calibrate()
3866 regmap_write(rt5659->regmap, RT5659_PWR_DIG_2, 0x0400); in rt5659_calibrate()
3868 regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0080); in rt5659_calibrate()
3870 regmap_write(rt5659->regmap, RT5659_DEPOP_1, 0x0009); in rt5659_calibrate()
3872 regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0f80); in rt5659_calibrate()
3874 regmap_write(rt5659->regmap, RT5659_HP_CHARGE_PUMP_1, 0x0e16); in rt5659_calibrate()
3877 /* Enalbe K ADC Power And Clock */ in rt5659_calibrate()
3878 regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0505); in rt5659_calibrate()
3880 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0184); in rt5659_calibrate()
3881 regmap_write(rt5659->regmap, RT5659_CALIB_ADC_CTRL, 0x3c05); in rt5659_calibrate()
3882 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c1); in rt5659_calibrate()
3885 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1); in rt5659_calibrate()
3886 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x5100); in rt5659_calibrate()
3887 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0014); in rt5659_calibrate()
3888 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0xd100); in rt5659_calibrate()
3891 /* Manual K ADC Offset */ in rt5659_calibrate()
3892 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1); in rt5659_calibrate()
3893 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x4900); in rt5659_calibrate()
3894 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0016); in rt5659_calibrate()
3895 regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, in rt5659_calibrate()
3900 regmap_read(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, &value); in rt5659_calibrate()
3907 dev_err(rt5659->component->dev, in rt5659_calibrate()
3916 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1); in rt5659_calibrate()
3917 regmap_write(rt5659->regmap, RT5659_HP_VOL, 0x0000); in rt5659_calibrate()
3918 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x4500); in rt5659_calibrate()
3919 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x001f); in rt5659_calibrate()
3920 regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, in rt5659_calibrate()
3925 regmap_read(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, &value); in rt5659_calibrate()
3932 dev_err(rt5659->component->dev, in rt5659_calibrate()
3940 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0000); in rt5659_calibrate()
3941 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c0); in rt5659_calibrate()
3945 regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x2021); in rt5659_calibrate()
3946 regmap_write(rt5659->regmap, RT5659_CLASSD_CTRL_1, 0x0260); in rt5659_calibrate()
3947 regmap_write(rt5659->regmap, RT5659_PWR_MIXER, 0x3000); in rt5659_calibrate()
3948 regmap_write(rt5659->regmap, RT5659_PWR_VOL, 0xc000); in rt5659_calibrate()
3949 regmap_write(rt5659->regmap, RT5659_A_DAC_MUX, 0x000c); in rt5659_calibrate()
3950 regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x8000); in rt5659_calibrate()
3951 regmap_write(rt5659->regmap, RT5659_SPO_VOL, 0x0808); in rt5659_calibrate()
3952 regmap_write(rt5659->regmap, RT5659_SPK_L_MIXER, 0x001e); in rt5659_calibrate()
3953 regmap_write(rt5659->regmap, RT5659_SPK_R_MIXER, 0x001e); in rt5659_calibrate()
3954 regmap_write(rt5659->regmap, RT5659_CLASSD_1, 0x0803); in rt5659_calibrate()
3955 regmap_write(rt5659->regmap, RT5659_CLASSD_2, 0x0554); in rt5659_calibrate()
3956 regmap_write(rt5659->regmap, RT5659_SPO_AMP_GAIN, 0x1103); in rt5659_calibrate()
3958 /* Enalbe K ADC Power And Clock */ in rt5659_calibrate()
3959 regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0909); in rt5659_calibrate()
3960 regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x0001, in rt5659_calibrate()
3964 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x0000); in rt5659_calibrate()
3965 regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x0021); in rt5659_calibrate()
3966 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_1, 0x3e80); in rt5659_calibrate()
3967 regmap_update_bits(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_1, in rt5659_calibrate()
3972 regmap_read(rt5659->regmap, in rt5659_calibrate()
3980 dev_err(rt5659->component->dev, in rt5659_calibrate()
3990 regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x0000); in rt5659_calibrate()
3991 regmap_write(rt5659->regmap, RT5659_MONOMIX_IN_GAIN, 0x021f); in rt5659_calibrate()
3992 regmap_write(rt5659->regmap, RT5659_MONO_OUT, 0x480a); in rt5659_calibrate()
3994 regmap_write(rt5659->regmap, RT5659_MONO_GAIN, 0x0003); in rt5659_calibrate()
3995 regmap_write(rt5659->regmap, RT5659_MONO_NG2_CTRL_5, 0x0009); in rt5659_calibrate()
3998 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x000f); in rt5659_calibrate()
3999 regmap_write(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e00); in rt5659_calibrate()
4000 regmap_update_bits(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1, in rt5659_calibrate()
4005 regmap_read(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1, in rt5659_calibrate()
4013 dev_err(rt5659->component->dev, in rt5659_calibrate()
4021 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x0003); in rt5659_calibrate()
4025 regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0808); in rt5659_calibrate()
4026 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0000); in rt5659_calibrate()
4027 regmap_write(rt5659->regmap, RT5659_CALIB_ADC_CTRL, 0x2005); in rt5659_calibrate()
4028 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c0); in rt5659_calibrate()
4029 regmap_write(rt5659->regmap, RT5659_DEPOP_1, 0x0000); in rt5659_calibrate()
4030 regmap_write(rt5659->regmap, RT5659_CLASSD_1, 0x0011); in rt5659_calibrate()
4031 regmap_write(rt5659->regmap, RT5659_CLASSD_2, 0x0150); in rt5659_calibrate()
4032 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xfe3e); in rt5659_calibrate()
4033 regmap_write(rt5659->regmap, RT5659_MONO_OUT, 0xc80a); in rt5659_calibrate()
4034 regmap_write(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e04); in rt5659_calibrate()
4035 regmap_write(rt5659->regmap, RT5659_PWR_MIXER, 0x0000); in rt5659_calibrate()
4036 regmap_write(rt5659->regmap, RT5659_PWR_VOL, 0x0000); in rt5659_calibrate()
4037 regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0000); in rt5659_calibrate()
4038 regmap_write(rt5659->regmap, RT5659_PWR_DIG_2, 0x0000); in rt5659_calibrate()
4039 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0x003e); in rt5659_calibrate()
4040 regmap_write(rt5659->regmap, RT5659_CLASSD_CTRL_1, 0x0060); in rt5659_calibrate()
4041 regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x2021); in rt5659_calibrate()
4042 regmap_write(rt5659->regmap, RT5659_GLB_CLK, 0x0000); in rt5659_calibrate()
4043 regmap_write(rt5659->regmap, RT5659_MICBIAS_2, 0x0080); in rt5659_calibrate()
4044 regmap_write(rt5659->regmap, RT5659_HP_VOL, 0x8080); in rt5659_calibrate()
4045 regmap_write(rt5659->regmap, RT5659_HP_CHARGE_PUMP_1, 0x0c16); in rt5659_calibrate()
4052 regmap_read(rt5659->regmap, RT5659_GPIO_STA, &value); in rt5659_intel_hd_header_probe_setup()
4054 rt5659->hda_hp_plugged = true; in rt5659_intel_hd_header_probe_setup()
4055 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1, in rt5659_intel_hd_header_probe_setup()
4058 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1, in rt5659_intel_hd_header_probe_setup()
4062 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1, in rt5659_intel_hd_header_probe_setup()
4066 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1, in rt5659_intel_hd_header_probe_setup()
4069 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_3, RT5659_PWR_LDO2, in rt5659_intel_hd_header_probe_setup()
4071 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_2, RT5659_PWR_MB1, in rt5659_intel_hd_header_probe_setup()
4073 regmap_update_bits(rt5659->regmap, RT5659_PWR_VOL, RT5659_PWR_MIC_DET, in rt5659_intel_hd_header_probe_setup()
4077 regmap_update_bits(rt5659->regmap, RT5659_4BTN_IL_CMD_2, in rt5659_intel_hd_header_probe_setup()
4079 regmap_read(rt5659->regmap, RT5659_4BTN_IL_CMD_1, &value); in rt5659_intel_hd_header_probe_setup()
4080 regmap_write(rt5659->regmap, RT5659_4BTN_IL_CMD_1, value); in rt5659_intel_hd_header_probe_setup()
4081 regmap_read(rt5659->regmap, RT5659_4BTN_IL_CMD_1, &value); in rt5659_intel_hd_header_probe_setup()
4084 rt5659->hda_mic_plugged = true; in rt5659_intel_hd_header_probe_setup()
4085 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2, in rt5659_intel_hd_header_probe_setup()
4088 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2, in rt5659_intel_hd_header_probe_setup()
4092 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2, in rt5659_intel_hd_header_probe_setup()
4099 struct rt5659_platform_data *pdata = dev_get_platdata(&i2c->dev); in rt5659_i2c_probe()
4104 rt5659 = devm_kzalloc(&i2c->dev, sizeof(struct rt5659_priv), in rt5659_i2c_probe()
4108 return -ENOMEM; in rt5659_i2c_probe()
4113 rt5659->pdata = *pdata; in rt5659_i2c_probe()
4115 rt5659_parse_dt(rt5659, &i2c->dev); in rt5659_i2c_probe()
4117 rt5659->gpiod_ldo1_en = devm_gpiod_get_optional(&i2c->dev, "ldo1-en", in rt5659_i2c_probe()
4119 if (IS_ERR(rt5659->gpiod_ldo1_en)) in rt5659_i2c_probe()
4120 dev_warn(&i2c->dev, "Request ldo1-en GPIO failed\n"); in rt5659_i2c_probe()
4122 rt5659->gpiod_reset = devm_gpiod_get_optional(&i2c->dev, "reset", in rt5659_i2c_probe()
4128 rt5659->regmap = devm_regmap_init_i2c(i2c, &rt5659_regmap); in rt5659_i2c_probe()
4129 if (IS_ERR(rt5659->regmap)) { in rt5659_i2c_probe()
4130 ret = PTR_ERR(rt5659->regmap); in rt5659_i2c_probe()
4131 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", in rt5659_i2c_probe()
4136 regmap_read(rt5659->regmap, RT5659_DEVICE_ID, &val); in rt5659_i2c_probe()
4138 dev_err(&i2c->dev, in rt5659_i2c_probe()
4140 return -ENODEV; in rt5659_i2c_probe()
4143 regmap_write(rt5659->regmap, RT5659_RESET, 0); in rt5659_i2c_probe()
4146 rt5659->mclk = devm_clk_get(&i2c->dev, "mclk"); in rt5659_i2c_probe()
4147 if (IS_ERR(rt5659->mclk)) { in rt5659_i2c_probe()
4148 if (PTR_ERR(rt5659->mclk) != -ENOENT) in rt5659_i2c_probe()
4149 return PTR_ERR(rt5659->mclk); in rt5659_i2c_probe()
4151 rt5659->mclk = NULL; in rt5659_i2c_probe()
4157 if (rt5659->pdata.in1_diff) in rt5659_i2c_probe()
4158 regmap_update_bits(rt5659->regmap, RT5659_IN1_IN2, in rt5659_i2c_probe()
4160 if (rt5659->pdata.in3_diff) in rt5659_i2c_probe()
4161 regmap_update_bits(rt5659->regmap, RT5659_IN3_IN4, in rt5659_i2c_probe()
4163 if (rt5659->pdata.in4_diff) in rt5659_i2c_probe()
4164 regmap_update_bits(rt5659->regmap, RT5659_IN3_IN4, in rt5659_i2c_probe()
4168 if (rt5659->pdata.dmic1_data_pin != RT5659_DMIC1_NULL || in rt5659_i2c_probe()
4169 rt5659->pdata.dmic2_data_pin != RT5659_DMIC2_NULL) { in rt5659_i2c_probe()
4170 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1, in rt5659_i2c_probe()
4173 switch (rt5659->pdata.dmic1_data_pin) { in rt5659_i2c_probe()
4175 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1, in rt5659_i2c_probe()
4180 regmap_update_bits(rt5659->regmap, in rt5659_i2c_probe()
4184 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1, in rt5659_i2c_probe()
4186 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1, in rt5659_i2c_probe()
4191 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1, in rt5659_i2c_probe()
4193 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1, in rt5659_i2c_probe()
4198 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1, in rt5659_i2c_probe()
4200 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1, in rt5659_i2c_probe()
4206 dev_dbg(&i2c->dev, "no DMIC1\n"); in rt5659_i2c_probe()
4210 switch (rt5659->pdata.dmic2_data_pin) { in rt5659_i2c_probe()
4212 regmap_update_bits(rt5659->regmap, in rt5659_i2c_probe()
4219 regmap_update_bits(rt5659->regmap, in rt5659_i2c_probe()
4223 regmap_update_bits(rt5659->regmap, in rt5659_i2c_probe()
4230 regmap_update_bits(rt5659->regmap, in rt5659_i2c_probe()
4234 regmap_update_bits(rt5659->regmap, in rt5659_i2c_probe()
4241 regmap_update_bits(rt5659->regmap, in rt5659_i2c_probe()
4245 regmap_update_bits(rt5659->regmap, in rt5659_i2c_probe()
4252 dev_dbg(&i2c->dev, "no DMIC2\n"); in rt5659_i2c_probe()
4257 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1, in rt5659_i2c_probe()
4266 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1, in rt5659_i2c_probe()
4271 switch (rt5659->pdata.jd_src) { in rt5659_i2c_probe()
4273 regmap_write(rt5659->regmap, RT5659_EJD_CTRL_1, 0xa880); in rt5659_i2c_probe()
4274 regmap_write(rt5659->regmap, RT5659_RC_CLK_CTRL, 0x9000); in rt5659_i2c_probe()
4275 regmap_write(rt5659->regmap, RT5659_GPIO_CTRL_1, 0xc800); in rt5659_i2c_probe()
4276 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1, in rt5659_i2c_probe()
4278 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_2, 0x0001); in rt5659_i2c_probe()
4279 regmap_write(rt5659->regmap, RT5659_IRQ_CTRL_2, 0x0040); in rt5659_i2c_probe()
4280 INIT_DELAYED_WORK(&rt5659->jack_detect_work, in rt5659_i2c_probe()
4284 regmap_write(rt5659->regmap, RT5659_GPIO_CTRL_3, 0x8000); in rt5659_i2c_probe()
4285 regmap_write(rt5659->regmap, RT5659_RC_CLK_CTRL, 0x0900); in rt5659_i2c_probe()
4286 regmap_write(rt5659->regmap, RT5659_EJD_CTRL_1, 0x70c0); in rt5659_i2c_probe()
4287 regmap_write(rt5659->regmap, RT5659_JD_CTRL_1, 0x2000); in rt5659_i2c_probe()
4288 regmap_write(rt5659->regmap, RT5659_IRQ_CTRL_1, 0x0040); in rt5659_i2c_probe()
4289 INIT_DELAYED_WORK(&rt5659->jack_detect_work, in rt5659_i2c_probe()
4297 if (i2c->irq) { in rt5659_i2c_probe()
4298 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, in rt5659_i2c_probe()
4302 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret); in rt5659_i2c_probe()
4305 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1, in rt5659_i2c_probe()
4309 return devm_snd_soc_register_component(&i2c->dev, in rt5659_i2c_probe()
4318 regmap_write(rt5659->regmap, RT5659_RESET, 0); in rt5659_i2c_shutdown()