240 	struct tx_macro *tx;  member
246 	struct tx_macro *tx;  member
276 	/* TX Macro */
420 	/* Update volatile list for tx/tx macros */  in tx_is_volatile_register()
593 static int tx_macro_mclk_enable(struct tx_macro *tx,  in tx_macro_mclk_enable()  argument
596 	struct regmap *regmap = tx->regmap;  in tx_macro_mclk_enable()
599 		if (tx->tx_mclk_users == 0) {  in tx_macro_mclk_enable()
611 		tx->tx_mclk_users++;  in tx_macro_mclk_enable()
613 		if (tx->tx_mclk_users <= 0) {  in tx_macro_mclk_enable()
614 			dev_err(tx->dev, "clock already disabled\n");  in tx_macro_mclk_enable()
615 			tx->tx_mclk_users = 0;  in tx_macro_mclk_enable()
618 		tx->tx_mclk_users--;  in tx_macro_mclk_enable()
619 		if (tx->tx_mclk_users == 0) {  in tx_macro_mclk_enable()
651 	struct tx_macro *tx;  in tx_macro_tx_hpf_corner_freq_callback()  local
658 	tx = hpf_work->tx;  in tx_macro_tx_hpf_corner_freq_callback()
659 	component = tx->component;  in tx_macro_tx_hpf_corner_freq_callback()
695 	struct tx_macro *tx;  in tx_macro_mute_update_callback()  local
701 	tx = tx_mute_dwork->tx;  in tx_macro_mute_update_callback()
702 	component = tx->component;  in tx_macro_mute_update_callback()
713 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);  in tx_macro_mclk_event()  local
717 		tx_macro_mclk_enable(tx, true);  in tx_macro_mclk_event()
720 		tx_macro_mclk_enable(tx, false);  in tx_macro_mclk_event()
738 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);  in tx_macro_put_dec_enum()  local
780 						tx->dmic_clk_div);  in tx_macro_put_dec_enum()
795 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);  in tx_macro_tx_mixer_get()  local
797 	if (test_bit(dec_id, &tx->active_ch_mask[dai_id]))  in tx_macro_tx_mixer_get()
815 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);  in tx_macro_tx_mixer_put()  local
818 		set_bit(dec_id, &tx->active_ch_mask[dai_id]);  in tx_macro_tx_mixer_put()
819 		tx->active_ch_cnt[dai_id]++;  in tx_macro_tx_mixer_put()
820 		tx->active_decimator[dai_id] = dec_id;  in tx_macro_tx_mixer_put()
822 		tx->active_ch_cnt[dai_id]--;  in tx_macro_tx_mixer_put()
823 		clear_bit(dec_id, &tx->active_ch_mask[dai_id]);  in tx_macro_tx_mixer_put()
824 		tx->active_decimator[dai_id] = -1;  in tx_macro_tx_mixer_put()
842 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);  in tx_macro_enable_dec()  local
863 							tx->dmic_clk_div);  in tx_macro_enable_dec()
868 					      tx->dec_mode[decimator]);  in tx_macro_enable_dec()
869 		/* Enable TX PGA Mute */  in tx_macro_enable_dec()
884 		tx->tx_hpf_work[decimator].hpf_cut_off_freq =  in tx_macro_enable_dec()
898 				   &tx->tx_mute_dwork[decimator].dwork,  in tx_macro_enable_dec()
900 		if (tx->tx_hpf_work[decimator].hpf_cut_off_freq != CF_MIN_3DB_150HZ) {  in tx_macro_enable_dec()
902 				&tx->tx_hpf_work[decimator].dwork,  in tx_macro_enable_dec()
927 		if (tx->bcs_enable) {  in tx_macro_enable_dec()
930 			tx->bcs_clk_en = true;  in tx_macro_enable_dec()
935 			tx->tx_hpf_work[decimator].hpf_cut_off_freq;  in tx_macro_enable_dec()
939 		    &tx->tx_hpf_work[decimator].dwork)) {  in tx_macro_enable_dec()
969 		cancel_delayed_work_sync(&tx->tx_mute_dwork[decimator].dwork);  in tx_macro_enable_dec()
978 		if (tx->bcs_enable) {  in tx_macro_enable_dec()
985 			tx->bcs_clk_en = false;  in tx_macro_enable_dec()
996 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);  in tx_macro_dec_mode_get()  local
1000 	ucontrol->value.integer.value[0] = tx->dec_mode[path];  in tx_macro_dec_mode_get()
1012 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);  in tx_macro_dec_mode_put()  local
1014 	tx->dec_mode[path] = value;  in tx_macro_dec_mode_put()
1023 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);  in tx_macro_get_bcs()  local
1025 	ucontrol->value.integer.value[0] = tx->bcs_enable;  in tx_macro_get_bcs()
1035 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);  in tx_macro_set_bcs()  local
1037 	tx->bcs_enable = value;  in tx_macro_set_bcs()
1049 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);  in tx_macro_hw_params()  local
1075 		dev_err(component->dev, "%s: Invalid TX sample rate: %d\n",  in tx_macro_hw_params()
1080 	for_each_set_bit(decimator, &tx->active_ch_mask[dai->id], TX_MACRO_DEC_MAX)  in tx_macro_hw_params()
1092 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);  in tx_macro_get_channel_map()  local
1098 		*tx_slot = tx->active_ch_mask[dai->id];  in tx_macro_get_channel_map()
1099 		*tx_num = tx->active_ch_cnt[dai->id];  in tx_macro_get_channel_map()
1110 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);  in tx_macro_digital_mute()  local
1113 	decimator = tx->active_decimator[dai->id];  in tx_macro_digital_mute()
1354 	SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux),
1355 	SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux),
1356 	SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux),
1357 	SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux),
1358 	SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux),
1359 	SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux),
1360 	SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux),
1361 	SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux),
1363 	SND_SOC_DAPM_INPUT("TX SWR_ADC0"),
1364 	SND_SOC_DAPM_INPUT("TX SWR_ADC1"),
1365 	SND_SOC_DAPM_INPUT("TX SWR_ADC2"),
1366 	SND_SOC_DAPM_INPUT("TX SWR_ADC3"),
1367 	SND_SOC_DAPM_INPUT("TX SWR_DMIC0"),
1368 	SND_SOC_DAPM_INPUT("TX SWR_DMIC1"),
1369 	SND_SOC_DAPM_INPUT("TX SWR_DMIC2"),
1370 	SND_SOC_DAPM_INPUT("TX SWR_DMIC3"),
1371 	SND_SOC_DAPM_INPUT("TX SWR_DMIC4"),
1372 	SND_SOC_DAPM_INPUT("TX SWR_DMIC5"),
1373 	SND_SOC_DAPM_INPUT("TX SWR_DMIC6"),
1374 	SND_SOC_DAPM_INPUT("TX SWR_DMIC7"),
1376 	SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM,
1382 	SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM,
1388 	SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM,
1394 	SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM,
1400 	SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM,
1406 	SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM,
1412 	SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM,
1418 	SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM,
1442 	{"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1443 	{"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1444 	{"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1445 	{"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1446 	{"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1447 	{"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1448 	{"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1449 	{"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1451 	{"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1452 	{"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1453 	{"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1454 	{"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1455 	{"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1456 	{"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1457 	{"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1458 	{"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1460 	{"TX_AIF3_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1461 	{"TX_AIF3_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1462 	{"TX_AIF3_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1463 	{"TX_AIF3_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1464 	{"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1465 	{"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1466 	{"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1467 	{"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1469 	{"TX DEC0 MUX", NULL, "TX_MCLK"},
1470 	{"TX DEC1 MUX", NULL, "TX_MCLK"},
1471 	{"TX DEC2 MUX", NULL, "TX_MCLK"},
1472 	{"TX DEC3 MUX", NULL, "TX_MCLK"},
1473 	{"TX DEC4 MUX", NULL, "TX_MCLK"},
1474 	{"TX DEC5 MUX", NULL, "TX_MCLK"},
1475 	{"TX DEC6 MUX", NULL, "TX_MCLK"},
1476 	{"TX DEC7 MUX", NULL, "TX_MCLK"},
1478 	{"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"},
1479 	{"TX SMIC MUX0", NULL, "TX_SWR_CLK"},
1480 	{"TX SMIC MUX0", "ADC0", "TX SWR_ADC0"},
1481 	{"TX SMIC MUX0", "ADC1", "TX SWR_ADC1"},
1482 	{"TX SMIC MUX0", "ADC2", "TX SWR_ADC2"},
1483 	{"TX SMIC MUX0", "ADC3", "TX SWR_ADC3"},
1484 	{"TX SMIC MUX0", "SWR_DMIC0", "TX SWR_DMIC0"},
1485 	{"TX SMIC MUX0", "SWR_DMIC1", "TX SWR_DMIC1"},
1486 	{"TX SMIC MUX0", "SWR_DMIC2", "TX SWR_DMIC2"},
1487 	{"TX SMIC MUX0", "SWR_DMIC3", "TX SWR_DMIC3"},
1488 	{"TX SMIC MUX0", "SWR_DMIC4", "TX SWR_DMIC4"},
1489 	{"TX SMIC MUX0", "SWR_DMIC5", "TX SWR_DMIC5"},
1490 	{"TX SMIC MUX0", "SWR_DMIC6", "TX SWR_DMIC6"},
1491 	{"TX SMIC MUX0", "SWR_DMIC7", "TX SWR_DMIC7"},
1493 	{"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"},
1494 	{"TX SMIC MUX1", NULL, "TX_SWR_CLK"},
1495 	{"TX SMIC MUX1", "ADC0", "TX SWR_ADC0"},
1496 	{"TX SMIC MUX1", "ADC1", "TX SWR_ADC1"},
1497 	{"TX SMIC MUX1", "ADC2", "TX SWR_ADC2"},
1498 	{"TX SMIC MUX1", "ADC3", "TX SWR_ADC3"},
1499 	{"TX SMIC MUX1", "SWR_DMIC0", "TX SWR_DMIC0"},
1500 	{"TX SMIC MUX1", "SWR_DMIC1", "TX SWR_DMIC1"},
1501 	{"TX SMIC MUX1", "SWR_DMIC2", "TX SWR_DMIC2"},
1502 	{"TX SMIC MUX1", "SWR_DMIC3", "TX SWR_DMIC3"},
1503 	{"TX SMIC MUX1", "SWR_DMIC4", "TX SWR_DMIC4"},
1504 	{"TX SMIC MUX1", "SWR_DMIC5", "TX SWR_DMIC5"},
1505 	{"TX SMIC MUX1", "SWR_DMIC6", "TX SWR_DMIC6"},
1506 	{"TX SMIC MUX1", "SWR_DMIC7", "TX SWR_DMIC7"},
1508 	{"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"},
1509 	{"TX SMIC MUX2", NULL, "TX_SWR_CLK"},
1510 	{"TX SMIC MUX2", "ADC0", "TX SWR_ADC0"},
1511 	{"TX SMIC MUX2", "ADC1", "TX SWR_ADC1"},
1512 	{"TX SMIC MUX2", "ADC2", "TX SWR_ADC2"},
1513 	{"TX SMIC MUX2", "ADC3", "TX SWR_ADC3"},
1514 	{"TX SMIC MUX2", "SWR_DMIC0", "TX SWR_DMIC0"},
1515 	{"TX SMIC MUX2", "SWR_DMIC1", "TX SWR_DMIC1"},
1516 	{"TX SMIC MUX2", "SWR_DMIC2", "TX SWR_DMIC2"},
1517 	{"TX SMIC MUX2", "SWR_DMIC3", "TX SWR_DMIC3"},
1518 	{"TX SMIC MUX2", "SWR_DMIC4", "TX SWR_DMIC4"},
1519 	{"TX SMIC MUX2", "SWR_DMIC5", "TX SWR_DMIC5"},
1520 	{"TX SMIC MUX2", "SWR_DMIC6", "TX SWR_DMIC6"},
1521 	{"TX SMIC MUX2", "SWR_DMIC7", "TX SWR_DMIC7"},
1523 	{"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"},
1524 	{"TX SMIC MUX3", NULL, "TX_SWR_CLK"},
1525 	{"TX SMIC MUX3", "ADC0", "TX SWR_ADC0"},
1526 	{"TX SMIC MUX3", "ADC1", "TX SWR_ADC1"},
1527 	{"TX SMIC MUX3", "ADC2", "TX SWR_ADC2"},
1528 	{"TX SMIC MUX3", "ADC3", "TX SWR_ADC3"},
1529 	{"TX SMIC MUX3", "SWR_DMIC0", "TX SWR_DMIC0"},
1530 	{"TX SMIC MUX3", "SWR_DMIC1", "TX SWR_DMIC1"},
1531 	{"TX SMIC MUX3", "SWR_DMIC2", "TX SWR_DMIC2"},
1532 	{"TX SMIC MUX3", "SWR_DMIC3", "TX SWR_DMIC3"},
1533 	{"TX SMIC MUX3", "SWR_DMIC4", "TX SWR_DMIC4"},
1534 	{"TX SMIC MUX3", "SWR_DMIC5", "TX SWR_DMIC5"},
1535 	{"TX SMIC MUX3", "SWR_DMIC6", "TX SWR_DMIC6"},
1536 	{"TX SMIC MUX3", "SWR_DMIC7", "TX SWR_DMIC7"},
1538 	{"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"},
1539 	{"TX SMIC MUX4", NULL, "TX_SWR_CLK"},
1540 	{"TX SMIC MUX4", "ADC0", "TX SWR_ADC0"},
1541 	{"TX SMIC MUX4", "ADC1", "TX SWR_ADC1"},
1542 	{"TX SMIC MUX4", "ADC2", "TX SWR_ADC2"},
1543 	{"TX SMIC MUX4", "ADC3", "TX SWR_ADC3"},
1544 	{"TX SMIC MUX4", "SWR_DMIC0", "TX SWR_DMIC0"},
1545 	{"TX SMIC MUX4", "SWR_DMIC1", "TX SWR_DMIC1"},
1546 	{"TX SMIC MUX4", "SWR_DMIC2", "TX SWR_DMIC2"},
1547 	{"TX SMIC MUX4", "SWR_DMIC3", "TX SWR_DMIC3"},
1548 	{"TX SMIC MUX4", "SWR_DMIC4", "TX SWR_DMIC4"},
1549 	{"TX SMIC MUX4", "SWR_DMIC5", "TX SWR_DMIC5"},
1550 	{"TX SMIC MUX4", "SWR_DMIC6", "TX SWR_DMIC6"},
1551 	{"TX SMIC MUX4", "SWR_DMIC7", "TX SWR_DMIC7"},
1553 	{"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"},
1554 	{"TX SMIC MUX5", NULL, "TX_SWR_CLK"},
1555 	{"TX SMIC MUX5", "ADC0", "TX SWR_ADC0"},
1556 	{"TX SMIC MUX5", "ADC1", "TX SWR_ADC1"},
1557 	{"TX SMIC MUX5", "ADC2", "TX SWR_ADC2"},
1558 	{"TX SMIC MUX5", "ADC3", "TX SWR_ADC3"},
1559 	{"TX SMIC MUX5", "SWR_DMIC0", "TX SWR_DMIC0"},
1560 	{"TX SMIC MUX5", "SWR_DMIC1", "TX SWR_DMIC1"},
1561 	{"TX SMIC MUX5", "SWR_DMIC2", "TX SWR_DMIC2"},
1562 	{"TX SMIC MUX5", "SWR_DMIC3", "TX SWR_DMIC3"},
1563 	{"TX SMIC MUX5", "SWR_DMIC4", "TX SWR_DMIC4"},
1564 	{"TX SMIC MUX5", "SWR_DMIC5", "TX SWR_DMIC5"},
1565 	{"TX SMIC MUX5", "SWR_DMIC6", "TX SWR_DMIC6"},
1566 	{"TX SMIC MUX5", "SWR_DMIC7", "TX SWR_DMIC7"},
1568 	{"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"},
1569 	{"TX SMIC MUX6", NULL, "TX_SWR_CLK"},
1570 	{"TX SMIC MUX6", "ADC0", "TX SWR_ADC0"},
1571 	{"TX SMIC MUX6", "ADC1", "TX SWR_ADC1"},
1572 	{"TX SMIC MUX6", "ADC2", "TX SWR_ADC2"},
1573 	{"TX SMIC MUX6", "ADC3", "TX SWR_ADC3"},
1574 	{"TX SMIC MUX6", "SWR_DMIC0", "TX SWR_DMIC0"},
1575 	{"TX SMIC MUX6", "SWR_DMIC1", "TX SWR_DMIC1"},
1576 	{"TX SMIC MUX6", "SWR_DMIC2", "TX SWR_DMIC2"},
1577 	{"TX SMIC MUX6", "SWR_DMIC3", "TX SWR_DMIC3"},
1578 	{"TX SMIC MUX6", "SWR_DMIC4", "TX SWR_DMIC4"},
1579 	{"TX SMIC MUX6", "SWR_DMIC5", "TX SWR_DMIC5"},
1580 	{"TX SMIC MUX6", "SWR_DMIC6", "TX SWR_DMIC6"},
1581 	{"TX SMIC MUX6", "SWR_DMIC7", "TX SWR_DMIC7"},
1583 	{"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"},
1584 	{"TX SMIC MUX7", NULL, "TX_SWR_CLK"},
1585 	{"TX SMIC MUX7", "ADC0", "TX SWR_ADC0"},
1586 	{"TX SMIC MUX7", "ADC1", "TX SWR_ADC1"},
1587 	{"TX SMIC MUX7", "ADC2", "TX SWR_ADC2"},
1588 	{"TX SMIC MUX7", "ADC3", "TX SWR_ADC3"},
1589 	{"TX SMIC MUX7", "SWR_DMIC0", "TX SWR_DMIC0"},
1590 	{"TX SMIC MUX7", "SWR_DMIC1", "TX SWR_DMIC1"},
1591 	{"TX SMIC MUX7", "SWR_DMIC2", "TX SWR_DMIC2"},
1592 	{"TX SMIC MUX7", "SWR_DMIC3", "TX SWR_DMIC3"},
1593 	{"TX SMIC MUX7", "SWR_DMIC4", "TX SWR_DMIC4"},
1594 	{"TX SMIC MUX7", "SWR_DMIC5", "TX SWR_DMIC5"},
1595 	{"TX SMIC MUX7", "SWR_DMIC6", "TX SWR_DMIC6"},
1596 	{"TX SMIC MUX7", "SWR_DMIC7", "TX SWR_DMIC7"},
1655 	struct tx_macro *tx = snd_soc_component_get_drvdata(comp);  in tx_macro_component_probe()  local
1658 	snd_soc_component_init_regmap(comp, tx->regmap);  in tx_macro_component_probe()
1661 		tx->tx_hpf_work[i].tx = tx;  in tx_macro_component_probe()
1662 		tx->tx_hpf_work[i].decimator = i;  in tx_macro_component_probe()
1663 		INIT_DELAYED_WORK(&tx->tx_hpf_work[i].dwork,  in tx_macro_component_probe()
1668 		tx->tx_mute_dwork[i].tx = tx;  in tx_macro_component_probe()
1669 		tx->tx_mute_dwork[i].decimator = i;  in tx_macro_component_probe()
1670 		INIT_DELAYED_WORK(&tx->tx_mute_dwork[i].dwork,  in tx_macro_component_probe()
1673 	tx->component = comp;  in tx_macro_component_probe()
1683 	struct tx_macro *tx = to_tx_macro(hw);  in swclk_gate_enable()  local
1684 	struct regmap *regmap = tx->regmap;  in swclk_gate_enable()
1686 	tx_macro_mclk_enable(tx, true);  in swclk_gate_enable()
1687 	if (tx->reset_swr)  in swclk_gate_enable()
1695 	if (tx->reset_swr)  in swclk_gate_enable()
1698 	tx->reset_swr = false;  in swclk_gate_enable()
1705 	struct tx_macro *tx = to_tx_macro(hw);  in swclk_gate_disable()  local
1706 	struct regmap *regmap = tx->regmap;  in swclk_gate_disable()
1711 	tx_macro_mclk_enable(tx, false);  in swclk_gate_disable()
1716 	struct tx_macro *tx = to_tx_macro(hw);  in swclk_gate_is_enabled()  local
1719 	regmap_read(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, &val);  in swclk_gate_is_enabled()
1739 static struct clk *tx_macro_register_mclk_output(struct tx_macro *tx)  in tx_macro_register_mclk_output()  argument
1741 	struct device *dev = tx->dev;  in tx_macro_register_mclk_output()
1744 	const char *clk_name = "lpass-tx-mclk";  in tx_macro_register_mclk_output()
1749 	parent_clk_name = __clk_get_name(tx->clks[2].clk);  in tx_macro_register_mclk_output()
1756 	tx->hw.init = &init;  in tx_macro_register_mclk_output()
1757 	hw = &tx->hw;  in tx_macro_register_mclk_output()
1758 	ret = clk_hw_register(tx->dev, hw);  in tx_macro_register_mclk_output()
1781 	struct tx_macro *tx;  in tx_macro_probe()  local
1785 	tx = devm_kzalloc(dev, sizeof(*tx), GFP_KERNEL);  in tx_macro_probe()
1786 	if (!tx)  in tx_macro_probe()
1789 	tx->clks[0].id = "macro";  in tx_macro_probe()
1790 	tx->clks[1].id = "dcodec";  in tx_macro_probe()
1791 	tx->clks[2].id = "mclk";  in tx_macro_probe()
1792 	tx->clks[3].id = "npl";  in tx_macro_probe()
1793 	tx->clks[4].id = "fsgen";  in tx_macro_probe()
1795 	ret = devm_clk_bulk_get(dev, TX_NUM_CLKS_MAX, tx->clks);  in tx_macro_probe()
1805 	tx->regmap = devm_regmap_init_mmio(dev, base, &tx_regmap_config);  in tx_macro_probe()
1807 	dev_set_drvdata(dev, tx);  in tx_macro_probe()
1809 	tx->reset_swr = true;  in tx_macro_probe()
1810 	tx->dev = dev;  in tx_macro_probe()
1813 	clk_set_rate(tx->clks[2].clk, MCLK_FREQ);  in tx_macro_probe()
1814 	clk_set_rate(tx->clks[3].clk, 2 * MCLK_FREQ);  in tx_macro_probe()
1816 	ret = clk_bulk_prepare_enable(TX_NUM_CLKS_MAX, tx->clks);  in tx_macro_probe()
1820 	tx_macro_register_mclk_output(tx);  in tx_macro_probe()
1829 	clk_bulk_disable_unprepare(TX_NUM_CLKS_MAX, tx->clks);  in tx_macro_probe()
1836 	struct tx_macro *tx = dev_get_drvdata(&pdev->dev);  in tx_macro_remove()  local
1840 	clk_bulk_disable_unprepare(TX_NUM_CLKS_MAX, tx->clks);  in tx_macro_remove()
1846 	{ .compatible = "qcom,sm8250-lpass-tx-macro" },
1862 MODULE_DESCRIPTION("TX macro driver");