Lines Matching full:rx
647 "ZERO", "RX INT0_1 MIX1",
651 "ZERO", "RX INT1_1 MIX1",
655 "ZERO", "RX INT2_1 MIX1",
659 "ZERO", "RX INT0_2 MUX",
663 "ZERO", "RX INT1_2 MUX",
667 "ZERO", "RX INT2_2 MUX",
765 SOC_DAPM_ENUM("RX MIX TX1_MUX Mux", rx_mix_tx1_mux_enum);
767 SOC_DAPM_ENUM("RX MIX TX2_MUX Mux", rx_mix_tx2_mux_enum);
827 SOC_DAPM_ENUM("RX MIX TX0_MUX Mux", rx_mix_tx0_mux_enum);
830 /* RX Macro */
1134 /* Update volatile list for rx/tx macros */ in rx_is_volatile_register()
1541 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_set_prim_interpolator_rate() local
1543 for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) { in rx_macro_set_prim_interpolator_rate()
1548 * to which interpolator input, the rx port in rx_macro_set_prim_interpolator_rate()
1586 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_set_mix_interpolator_rate() local
1588 for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) { in rx_macro_set_mix_interpolator_rate()
1632 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_hw_params() local
1643 rx->bit_width[dai->id] = params_width(params); in rx_macro_hw_params()
1656 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_get_channel_map() local
1664 for_each_set_bit(temp, &rx->active_ch_mask[dai->id], in rx_macro_get_channel_map()
1685 *rx_num = rx->active_ch_cnt[dai->id]; in rx_macro_get_channel_map()
1848 static void rx_macro_mclk_enable(struct rx_macro *rx, bool mclk_enable) in rx_macro_mclk_enable() argument
1850 struct regmap *regmap = rx->regmap; in rx_macro_mclk_enable()
1853 if (rx->rx_mclk_users == 0) { in rx_macro_mclk_enable()
1867 rx->rx_mclk_users++; in rx_macro_mclk_enable()
1869 if (rx->rx_mclk_users <= 0) { in rx_macro_mclk_enable()
1870 dev_err(rx->dev, "%s: clock already disabled\n", __func__); in rx_macro_mclk_enable()
1871 rx->rx_mclk_users = 0; in rx_macro_mclk_enable()
1874 rx->rx_mclk_users--; in rx_macro_mclk_enable()
1875 if (rx->rx_mclk_users == 0) { in rx_macro_mclk_enable()
1892 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_mclk_event() local
1897 rx_macro_mclk_enable(rx, true); in rx_macro_mclk_event()
1900 rx_macro_mclk_enable(rx, false); in rx_macro_mclk_event()
1979 struct rx_macro *rx, in rx_macro_config_compander() argument
2005 if (!rx->comp_enabled[comp]) in rx_macro_config_compander()
2035 struct rx_macro *rx, in rx_macro_load_compander_coeff() argument
2042 if (!rx->comp_enabled[comp]) in rx_macro_load_compander_coeff()
2056 hph_pwr_mode = rx->hph_pwr_mode; in rx_macro_load_compander_coeff()
2072 struct rx_macro *rx, bool enable) in rx_macro_enable_softclip_clk() argument
2075 if (rx->softclip_clk_users == 0) in rx_macro_enable_softclip_clk()
2078 rx->softclip_clk_users++; in rx_macro_enable_softclip_clk()
2080 rx->softclip_clk_users--; in rx_macro_enable_softclip_clk()
2081 if (rx->softclip_clk_users == 0) in rx_macro_enable_softclip_clk()
2088 struct rx_macro *rx, int event) in rx_macro_config_softclip() argument
2091 if (!rx->is_softclip_on) in rx_macro_config_softclip()
2096 rx_macro_enable_softclip_clk(component, rx, true); in rx_macro_config_softclip()
2105 rx_macro_enable_softclip_clk(component, rx, false); in rx_macro_config_softclip()
2112 struct rx_macro *rx, int event) in rx_macro_config_aux_hpf() argument
2116 if (!rx->is_aux_hpf_on) in rx_macro_config_aux_hpf()
2130 static inline void rx_macro_enable_clsh_block(struct rx_macro *rx, bool enable) in rx_macro_enable_clsh_block() argument
2132 if ((enable && ++rx->clsh_users == 1) || (!enable && --rx->clsh_users == 0)) in rx_macro_enable_clsh_block()
2133 snd_soc_component_update_bits(rx->component, CDC_RX_CLSH_CRC, in rx_macro_enable_clsh_block()
2135 if (rx->clsh_users < 0) in rx_macro_enable_clsh_block()
2136 rx->clsh_users = 0; in rx_macro_enable_clsh_block()
2140 struct rx_macro *rx, in rx_macro_config_classh() argument
2144 rx_macro_enable_clsh_block(rx, false); in rx_macro_config_classh()
2151 rx_macro_enable_clsh_block(rx, true); in rx_macro_config_classh()
2164 if (rx->is_ear_mode_on) in rx_macro_config_classh()
2180 if (rx->is_ear_mode_on) in rx_macro_config_classh()
2245 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_get_compander() local
2247 ucontrol->value.integer.value[0] = rx->comp_enabled[comp]; in rx_macro_get_compander()
2257 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_set_compander() local
2259 rx->comp_enabled[comp] = value; in rx_macro_set_compander()
2269 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_mux_get() local
2272 rx->rx_port_value[widget->shift]; in rx_macro_mux_get()
2285 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_mux_put() local
2287 aif_rst = rx->rx_port_value[widget->shift]; in rx_macro_mux_put()
2298 rx->rx_port_value[widget->shift] = rx_port_value; in rx_macro_mux_put()
2302 if (rx->active_ch_cnt[aif_rst]) { in rx_macro_mux_put()
2304 &rx->active_ch_mask[aif_rst]); in rx_macro_mux_put()
2305 rx->active_ch_cnt[aif_rst]--; in rx_macro_mux_put()
2313 &rx->active_ch_mask[rx_port_value]); in rx_macro_mux_put()
2314 rx->active_ch_cnt[rx_port_value]++; in rx_macro_mux_put()
2353 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_get_ear_mode() local
2355 ucontrol->value.integer.value[0] = rx->is_ear_mode_on; in rx_macro_get_ear_mode()
2363 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_put_ear_mode() local
2365 rx->is_ear_mode_on = (!ucontrol->value.integer.value[0] ? false : true); in rx_macro_put_ear_mode()
2373 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_get_hph_hd2_mode() local
2375 ucontrol->value.integer.value[0] = rx->hph_hd2_mode; in rx_macro_get_hph_hd2_mode()
2383 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_put_hph_hd2_mode() local
2385 rx->hph_hd2_mode = ucontrol->value.integer.value[0]; in rx_macro_put_hph_hd2_mode()
2393 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_get_hph_pwr_mode() local
2395 ucontrol->value.integer.value[0] = rx->hph_pwr_mode; in rx_macro_get_hph_pwr_mode()
2403 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_put_hph_pwr_mode() local
2405 rx->hph_pwr_mode = ucontrol->value.integer.value[0]; in rx_macro_put_hph_pwr_mode()
2413 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_soft_clip_enable_get() local
2415 ucontrol->value.integer.value[0] = rx->is_softclip_on; in rx_macro_soft_clip_enable_get()
2424 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_soft_clip_enable_put() local
2426 rx->is_softclip_on = ucontrol->value.integer.value[0]; in rx_macro_soft_clip_enable_put()
2435 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_aux_hpf_mode_get() local
2437 ucontrol->value.integer.value[0] = rx->is_aux_hpf_on; in rx_macro_aux_hpf_mode_get()
2446 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_aux_hpf_mode_put() local
2448 rx->is_aux_hpf_on = ucontrol->value.integer.value[0]; in rx_macro_aux_hpf_mode_put()
2454 struct rx_macro *rx, in rx_macro_hphdelay_lutbypass() argument
2475 if (rx->is_ear_mode_on) in rx_macro_hphdelay_lutbypass()
2487 if (rx->hph_pwr_mode) in rx_macro_hphdelay_lutbypass()
2509 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_enable_interp_clk() local
2518 if (rx->main_clk_users[interp_idx] == 0) { in rx_macro_enable_interp_clk()
2526 rx_macro_load_compander_coeff(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2527 if (rx->hph_hd2_mode) in rx_macro_enable_interp_clk()
2529 rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2530 rx_macro_config_compander(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2532 rx_macro_config_softclip(component, rx, event); in rx_macro_enable_interp_clk()
2533 rx_macro_config_aux_hpf(component, rx, event); in rx_macro_enable_interp_clk()
2535 rx_macro_config_classh(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2537 rx->main_clk_users[interp_idx]++; in rx_macro_enable_interp_clk()
2541 rx->main_clk_users[interp_idx]--; in rx_macro_enable_interp_clk()
2542 if (rx->main_clk_users[interp_idx] <= 0) { in rx_macro_enable_interp_clk()
2543 rx->main_clk_users[interp_idx] = 0; in rx_macro_enable_interp_clk()
2563 rx_macro_config_classh(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2564 rx_macro_config_compander(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2566 rx_macro_config_softclip(component, rx, event); in rx_macro_enable_interp_clk()
2567 rx_macro_config_aux_hpf(component, rx, event); in rx_macro_enable_interp_clk()
2569 rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2570 if (rx->hph_hd2_mode) in rx_macro_enable_interp_clk()
2575 return rx->main_clk_users[interp_idx]; in rx_macro_enable_interp_clk()
2901 if (!(strcmp(w->name, "RX MIX TX0 MUX"))) in rx_macro_enable_echo()
2903 else if (!(strcmp(w->name, "RX MIX TX1 MUX"))) in rx_macro_enable_echo()
2908 if (!(strcmp(w->name, "RX MIX TX2 MUX"))) in rx_macro_enable_echo()
2928 SND_SOC_DAPM_AIF_IN("RX AIF1 PB", "RX_MACRO_AIF1 Playback", 0,
2931 SND_SOC_DAPM_AIF_IN("RX AIF2 PB", "RX_MACRO_AIF2 Playback", 0,
2934 SND_SOC_DAPM_AIF_IN("RX AIF3 PB", "RX_MACRO_AIF3 Playback", 0,
2937 SND_SOC_DAPM_AIF_IN("RX AIF4 PB", "RX_MACRO_AIF4 Playback", 0,
2940 SND_SOC_DAPM_AIF_OUT("RX AIF_ECHO", "RX_AIF_ECHO Capture", 0,
2972 SND_SOC_DAPM_MUX_E("RX MIX TX0 MUX", SND_SOC_NOPM,
2976 SND_SOC_DAPM_MUX_E("RX MIX TX1 MUX", SND_SOC_NOPM,
2980 SND_SOC_DAPM_MUX_E("RX MIX TX2 MUX", SND_SOC_NOPM,
2996 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
2998 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
3001 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
3005 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
3009 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_AUX, 0,
3014 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp0_mux),
3015 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp1_mux),
3016 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp2_mux),
3017 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp0_mux),
3018 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp1_mux),
3019 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp2_mux),
3020 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp0_mux),
3021 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp1_mux),
3022 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp2_mux),
3024 SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
3028 SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
3032 SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_AUX, 0,
3037 SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
3039 SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
3041 SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
3044 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3045 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3046 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3047 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3048 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3049 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3051 SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", SND_SOC_NOPM, INTERP_HPHL,
3054 SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", SND_SOC_NOPM, INTERP_HPHR,
3057 SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", SND_SOC_NOPM, INTERP_AUX,
3061 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3062 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3063 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3079 {"RX AIF1 PB", NULL, "RX_MCLK"},
3080 {"RX AIF2 PB", NULL, "RX_MCLK"},
3081 {"RX AIF3 PB", NULL, "RX_MCLK"},
3082 {"RX AIF4 PB", NULL, "RX_MCLK"},
3084 {"RX_MACRO RX0 MUX", "AIF1_PB", "RX AIF1 PB"},
3085 {"RX_MACRO RX1 MUX", "AIF1_PB", "RX AIF1 PB"},
3086 {"RX_MACRO RX2 MUX", "AIF1_PB", "RX AIF1 PB"},
3087 {"RX_MACRO RX3 MUX", "AIF1_PB", "RX AIF1 PB"},
3088 {"RX_MACRO RX4 MUX", "AIF1_PB", "RX AIF1 PB"},
3089 {"RX_MACRO RX5 MUX", "AIF1_PB", "RX AIF1 PB"},
3091 {"RX_MACRO RX0 MUX", "AIF2_PB", "RX AIF2 PB"},
3092 {"RX_MACRO RX1 MUX", "AIF2_PB", "RX AIF2 PB"},
3093 {"RX_MACRO RX2 MUX", "AIF2_PB", "RX AIF2 PB"},
3094 {"RX_MACRO RX3 MUX", "AIF2_PB", "RX AIF2 PB"},
3095 {"RX_MACRO RX4 MUX", "AIF2_PB", "RX AIF2 PB"},
3096 {"RX_MACRO RX5 MUX", "AIF2_PB", "RX AIF2 PB"},
3098 {"RX_MACRO RX0 MUX", "AIF3_PB", "RX AIF3 PB"},
3099 {"RX_MACRO RX1 MUX", "AIF3_PB", "RX AIF3 PB"},
3100 {"RX_MACRO RX2 MUX", "AIF3_PB", "RX AIF3 PB"},
3101 {"RX_MACRO RX3 MUX", "AIF3_PB", "RX AIF3 PB"},
3102 {"RX_MACRO RX4 MUX", "AIF3_PB", "RX AIF3 PB"},
3103 {"RX_MACRO RX5 MUX", "AIF3_PB", "RX AIF3 PB"},
3105 {"RX_MACRO RX0 MUX", "AIF4_PB", "RX AIF4 PB"},
3106 {"RX_MACRO RX1 MUX", "AIF4_PB", "RX AIF4 PB"},
3107 {"RX_MACRO RX2 MUX", "AIF4_PB", "RX AIF4 PB"},
3108 {"RX_MACRO RX3 MUX", "AIF4_PB", "RX AIF4 PB"},
3109 {"RX_MACRO RX4 MUX", "AIF4_PB", "RX AIF4 PB"},
3110 {"RX_MACRO RX5 MUX", "AIF4_PB", "RX AIF4 PB"},
3119 {"RX INT0_1 MIX1 INP0", "RX0", "RX_RX0"},
3120 {"RX INT0_1 MIX1 INP0", "RX1", "RX_RX1"},
3121 {"RX INT0_1 MIX1 INP0", "RX2", "RX_RX2"},
3122 {"RX INT0_1 MIX1 INP0", "RX3", "RX_RX3"},
3123 {"RX INT0_1 MIX1 INP0", "RX4", "RX_RX4"},
3124 {"RX INT0_1 MIX1 INP0", "RX5", "RX_RX5"},
3125 {"RX INT0_1 MIX1 INP0", "IIR0", "IIR0"},
3126 {"RX INT0_1 MIX1 INP0", "IIR1", "IIR1"},
3127 {"RX INT0_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3128 {"RX INT0_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3129 {"RX INT0_1 MIX1 INP1", "RX0", "RX_RX0"},
3130 {"RX INT0_1 MIX1 INP1", "RX1", "RX_RX1"},
3131 {"RX INT0_1 MIX1 INP1", "RX2", "RX_RX2"},
3132 {"RX INT0_1 MIX1 INP1", "RX3", "RX_RX3"},
3133 {"RX INT0_1 MIX1 INP1", "RX4", "RX_RX4"},
3134 {"RX INT0_1 MIX1 INP1", "RX5", "RX_RX5"},
3135 {"RX INT0_1 MIX1 INP1", "IIR0", "IIR0"},
3136 {"RX INT0_1 MIX1 INP1", "IIR1", "IIR1"},
3137 {"RX INT0_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3138 {"RX INT0_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3139 {"RX INT0_1 MIX1 INP2", "RX0", "RX_RX0"},
3140 {"RX INT0_1 MIX1 INP2", "RX1", "RX_RX1"},
3141 {"RX INT0_1 MIX1 INP2", "RX2", "RX_RX2"},
3142 {"RX INT0_1 MIX1 INP2", "RX3", "RX_RX3"},
3143 {"RX INT0_1 MIX1 INP2", "RX4", "RX_RX4"},
3144 {"RX INT0_1 MIX1 INP2", "RX5", "RX_RX5"},
3145 {"RX INT0_1 MIX1 INP2", "IIR0", "IIR0"},
3146 {"RX INT0_1 MIX1 INP2", "IIR1", "IIR1"},
3147 {"RX INT0_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3148 {"RX INT0_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3150 {"RX INT1_1 MIX1 INP0", "RX0", "RX_RX0"},
3151 {"RX INT1_1 MIX1 INP0", "RX1", "RX_RX1"},
3152 {"RX INT1_1 MIX1 INP0", "RX2", "RX_RX2"},
3153 {"RX INT1_1 MIX1 INP0", "RX3", "RX_RX3"},
3154 {"RX INT1_1 MIX1 INP0", "RX4", "RX_RX4"},
3155 {"RX INT1_1 MIX1 INP0", "RX5", "RX_RX5"},
3156 {"RX INT1_1 MIX1 INP0", "IIR0", "IIR0"},
3157 {"RX INT1_1 MIX1 INP0", "IIR1", "IIR1"},
3158 {"RX INT1_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3159 {"RX INT1_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3160 {"RX INT1_1 MIX1 INP1", "RX0", "RX_RX0"},
3161 {"RX INT1_1 MIX1 INP1", "RX1", "RX_RX1"},
3162 {"RX INT1_1 MIX1 INP1", "RX2", "RX_RX2"},
3163 {"RX INT1_1 MIX1 INP1", "RX3", "RX_RX3"},
3164 {"RX INT1_1 MIX1 INP1", "RX4", "RX_RX4"},
3165 {"RX INT1_1 MIX1 INP1", "RX5", "RX_RX5"},
3166 {"RX INT1_1 MIX1 INP1", "IIR0", "IIR0"},
3167 {"RX INT1_1 MIX1 INP1", "IIR1", "IIR1"},
3168 {"RX INT1_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3169 {"RX INT1_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3170 {"RX INT1_1 MIX1 INP2", "RX0", "RX_RX0"},
3171 {"RX INT1_1 MIX1 INP2", "RX1", "RX_RX1"},
3172 {"RX INT1_1 MIX1 INP2", "RX2", "RX_RX2"},
3173 {"RX INT1_1 MIX1 INP2", "RX3", "RX_RX3"},
3174 {"RX INT1_1 MIX1 INP2", "RX4", "RX_RX4"},
3175 {"RX INT1_1 MIX1 INP2", "RX5", "RX_RX5"},
3176 {"RX INT1_1 MIX1 INP2", "IIR0", "IIR0"},
3177 {"RX INT1_1 MIX1 INP2", "IIR1", "IIR1"},
3178 {"RX INT1_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3179 {"RX INT1_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3181 {"RX INT2_1 MIX1 INP0", "RX0", "RX_RX0"},
3182 {"RX INT2_1 MIX1 INP0", "RX1", "RX_RX1"},
3183 {"RX INT2_1 MIX1 INP0", "RX2", "RX_RX2"},
3184 {"RX INT2_1 MIX1 INP0", "RX3", "RX_RX3"},
3185 {"RX INT2_1 MIX1 INP0", "RX4", "RX_RX4"},
3186 {"RX INT2_1 MIX1 INP0", "RX5", "RX_RX5"},
3187 {"RX INT2_1 MIX1 INP0", "IIR0", "IIR0"},
3188 {"RX INT2_1 MIX1 INP0", "IIR1", "IIR1"},
3189 {"RX INT2_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3190 {"RX INT2_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3191 {"RX INT2_1 MIX1 INP1", "RX0", "RX_RX0"},
3192 {"RX INT2_1 MIX1 INP1", "RX1", "RX_RX1"},
3193 {"RX INT2_1 MIX1 INP1", "RX2", "RX_RX2"},
3194 {"RX INT2_1 MIX1 INP1", "RX3", "RX_RX3"},
3195 {"RX INT2_1 MIX1 INP1", "RX4", "RX_RX4"},
3196 {"RX INT2_1 MIX1 INP1", "RX5", "RX_RX5"},
3197 {"RX INT2_1 MIX1 INP1", "IIR0", "IIR0"},
3198 {"RX INT2_1 MIX1 INP1", "IIR1", "IIR1"},
3199 {"RX INT2_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3200 {"RX INT2_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3201 {"RX INT2_1 MIX1 INP2", "RX0", "RX_RX0"},
3202 {"RX INT2_1 MIX1 INP2", "RX1", "RX_RX1"},
3203 {"RX INT2_1 MIX1 INP2", "RX2", "RX_RX2"},
3204 {"RX INT2_1 MIX1 INP2", "RX3", "RX_RX3"},
3205 {"RX INT2_1 MIX1 INP2", "RX4", "RX_RX4"},
3206 {"RX INT2_1 MIX1 INP2", "RX5", "RX_RX5"},
3207 {"RX INT2_1 MIX1 INP2", "IIR0", "IIR0"},
3208 {"RX INT2_1 MIX1 INP2", "IIR1", "IIR1"},
3209 {"RX INT2_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3210 {"RX INT2_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3212 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP0"},
3213 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP1"},
3214 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP2"},
3215 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP0"},
3216 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP1"},
3217 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP2"},
3218 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP0"},
3219 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP1"},
3220 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP2"},
3222 {"RX MIX TX0 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3223 {"RX MIX TX0 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3224 {"RX MIX TX0 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3225 {"RX MIX TX1 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3226 {"RX MIX TX1 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3227 {"RX MIX TX1 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3228 {"RX MIX TX2 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3229 {"RX MIX TX2 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3230 {"RX MIX TX2 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3231 {"RX AIF_ECHO", NULL, "RX MIX TX0 MUX"},
3232 {"RX AIF_ECHO", NULL, "RX MIX TX1 MUX"},
3233 {"RX AIF_ECHO", NULL, "RX MIX TX2 MUX"},
3234 {"RX AIF_ECHO", NULL, "RX_MCLK"},
3237 {"RX INT0_2 MUX", "RX0", "RX_RX0"},
3238 {"RX INT0_2 MUX", "RX1", "RX_RX1"},
3239 {"RX INT0_2 MUX", "RX2", "RX_RX2"},
3240 {"RX INT0_2 MUX", "RX3", "RX_RX3"},
3241 {"RX INT0_2 MUX", "RX4", "RX_RX4"},
3242 {"RX INT0_2 MUX", "RX5", "RX_RX5"},
3243 {"RX INT0_2 INTERP", NULL, "RX INT0_2 MUX"},
3244 {"RX INT0 SEC MIX", NULL, "RX INT0_2 INTERP"},
3247 {"RX INT1_2 MUX", "RX0", "RX_RX0"},
3248 {"RX INT1_2 MUX", "RX1", "RX_RX1"},
3249 {"RX INT1_2 MUX", "RX2", "RX_RX2"},
3250 {"RX INT1_2 MUX", "RX3", "RX_RX3"},
3251 {"RX INT1_2 MUX", "RX4", "RX_RX4"},
3252 {"RX INT1_2 MUX", "RX5", "RX_RX5"},
3253 {"RX INT1_2 INTERP", NULL, "RX INT1_2 MUX"},
3254 {"RX INT1 SEC MIX", NULL, "RX INT1_2 INTERP"},
3257 {"RX INT2_2 MUX", "RX0", "RX_RX0"},
3258 {"RX INT2_2 MUX", "RX1", "RX_RX1"},
3259 {"RX INT2_2 MUX", "RX2", "RX_RX2"},
3260 {"RX INT2_2 MUX", "RX3", "RX_RX3"},
3261 {"RX INT2_2 MUX", "RX4", "RX_RX4"},
3262 {"RX INT2_2 MUX", "RX5", "RX_RX5"},
3263 {"RX INT2_2 INTERP", NULL, "RX INT2_2 MUX"},
3264 {"RX INT2 SEC MIX", NULL, "RX INT2_2 INTERP"},
3266 {"RX INT0_1 INTERP", NULL, "RX INT0_1 MIX1"},
3267 {"RX INT0 SEC MIX", NULL, "RX INT0_1 INTERP"},
3268 {"RX INT0 MIX2", NULL, "RX INT0 SEC MIX"},
3269 {"RX INT0 MIX2", NULL, "RX INT0 MIX2 INP"},
3270 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
3271 {"HPHL_OUT", NULL, "RX INT0 DEM MUX"},
3274 {"RX INT1_1 INTERP", NULL, "RX INT1_1 MIX1"},
3275 {"RX INT1 SEC MIX", NULL, "RX INT1_1 INTERP"},
3276 {"RX INT1 MIX2", NULL, "RX INT1 SEC MIX"},
3277 {"RX INT1 MIX2", NULL, "RX INT1 MIX2 INP"},
3278 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX2"},
3279 {"HPHR_OUT", NULL, "RX INT1 DEM MUX"},
3282 {"RX INT2_1 INTERP", NULL, "RX INT2_1 MIX1"},
3284 {"RX INT2 SEC MIX", NULL, "RX INT2_1 INTERP"},
3285 {"RX INT2 MIX2", NULL, "RX INT2 SEC MIX"},
3286 {"RX INT2 MIX2", NULL, "RX INT2 MIX2 INP"},
3287 {"AUX_OUT", NULL, "RX INT2 MIX2"},
3384 {"RX INT0 MIX2 INP", "SRC0", "SRC0"},
3385 {"RX INT0 MIX2 INP", "SRC1", "SRC1"},
3386 {"RX INT1 MIX2 INP", "SRC0", "SRC0"},
3387 {"RX INT1 MIX2 INP", "SRC1", "SRC1"},
3388 {"RX INT2 MIX2 INP", "SRC0", "SRC0"},
3389 {"RX INT2 MIX2 INP", "SRC1", "SRC1"},
3394 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_component_probe() local
3396 snd_soc_component_init_regmap(component, rx->regmap); in rx_macro_component_probe()
3417 rx->component = component; in rx_macro_component_probe()
3424 struct rx_macro *rx = to_rx_macro(hw); in swclk_gate_enable() local
3426 rx_macro_mclk_enable(rx, true); in swclk_gate_enable()
3427 if (rx->reset_swr) in swclk_gate_enable()
3428 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in swclk_gate_enable()
3432 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in swclk_gate_enable()
3435 if (rx->reset_swr) in swclk_gate_enable()
3436 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in swclk_gate_enable()
3438 rx->reset_swr = false; in swclk_gate_enable()
3445 struct rx_macro *rx = to_rx_macro(hw); in swclk_gate_disable() local
3447 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in swclk_gate_disable()
3450 rx_macro_mclk_enable(rx, false); in swclk_gate_disable()
3455 struct rx_macro *rx = to_rx_macro(hw); in swclk_gate_is_enabled() local
3458 regmap_read(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, &val); in swclk_gate_is_enabled()
3478 static struct clk *rx_macro_register_mclk_output(struct rx_macro *rx) in rx_macro_register_mclk_output() argument
3480 struct device *dev = rx->dev; in rx_macro_register_mclk_output()
3483 const char *clk_name = "lpass-rx-mclk"; in rx_macro_register_mclk_output()
3488 parent_clk_name = __clk_get_name(rx->clks[2].clk); in rx_macro_register_mclk_output()
3495 rx->hw.init = &init; in rx_macro_register_mclk_output()
3496 hw = &rx->hw; in rx_macro_register_mclk_output()
3497 ret = clk_hw_register(rx->dev, hw); in rx_macro_register_mclk_output()
3507 .name = "RX-MACRO",
3520 struct rx_macro *rx; in rx_macro_probe() local
3524 rx = devm_kzalloc(dev, sizeof(*rx), GFP_KERNEL); in rx_macro_probe()
3525 if (!rx) in rx_macro_probe()
3528 rx->clks[0].id = "macro"; in rx_macro_probe()
3529 rx->clks[1].id = "dcodec"; in rx_macro_probe()
3530 rx->clks[2].id = "mclk"; in rx_macro_probe()
3531 rx->clks[3].id = "npl"; in rx_macro_probe()
3532 rx->clks[4].id = "fsgen"; in rx_macro_probe()
3534 ret = devm_clk_bulk_get(dev, RX_NUM_CLKS_MAX, rx->clks); in rx_macro_probe()
3536 dev_err(dev, "Error getting RX Clocks (%d)\n", ret); in rx_macro_probe()
3544 rx->regmap = devm_regmap_init_mmio(dev, base, &rx_regmap_config); in rx_macro_probe()
3546 dev_set_drvdata(dev, rx); in rx_macro_probe()
3548 rx->reset_swr = true; in rx_macro_probe()
3549 rx->dev = dev; in rx_macro_probe()
3552 clk_set_rate(rx->clks[2].clk, MCLK_FREQ); in rx_macro_probe()
3553 clk_set_rate(rx->clks[3].clk, 2 * MCLK_FREQ); in rx_macro_probe()
3555 ret = clk_bulk_prepare_enable(RX_NUM_CLKS_MAX, rx->clks); in rx_macro_probe()
3559 rx_macro_register_mclk_output(rx); in rx_macro_probe()
3565 clk_bulk_disable_unprepare(RX_NUM_CLKS_MAX, rx->clks); in rx_macro_probe()
3572 struct rx_macro *rx = dev_get_drvdata(&pdev->dev); in rx_macro_remove() local
3575 clk_bulk_disable_unprepare(RX_NUM_CLKS_MAX, rx->clks); in rx_macro_remove()
3580 { .compatible = "qcom,sm8250-lpass-rx-macro" },
3597 MODULE_DESCRIPTION("RX macro driver");