Lines Matching +full:0 +full:x1900
17 #define CS42L42_PAGE_REGISTER 0x00 /* Page Select Register */
18 #define CS42L42_WIN_START 0x00
19 #define CS42L42_WIN_LEN 0x100
20 #define CS42L42_RANGE_MIN 0x00
21 #define CS42L42_RANGE_MAX 0x7F
23 #define CS42L42_PAGE_10 0x1000
24 #define CS42L42_PAGE_11 0x1100
25 #define CS42L42_PAGE_12 0x1200
26 #define CS42L42_PAGE_13 0x1300
27 #define CS42L42_PAGE_15 0x1500
28 #define CS42L42_PAGE_19 0x1900
29 #define CS42L42_PAGE_1B 0x1B00
30 #define CS42L42_PAGE_1C 0x1C00
31 #define CS42L42_PAGE_1D 0x1D00
32 #define CS42L42_PAGE_1F 0x1F00
33 #define CS42L42_PAGE_20 0x2000
34 #define CS42L42_PAGE_21 0x2100
35 #define CS42L42_PAGE_23 0x2300
36 #define CS42L42_PAGE_24 0x2400
37 #define CS42L42_PAGE_25 0x2500
38 #define CS42L42_PAGE_26 0x2600
39 #define CS42L42_PAGE_28 0x2800
40 #define CS42L42_PAGE_29 0x2900
41 #define CS42L42_PAGE_2A 0x2A00
42 #define CS42L42_PAGE_30 0x3000
44 #define CS42L42_CHIP_ID 0x42A42
46 /* Page 0x10 Global Registers */
47 #define CS42L42_DEVID_AB (CS42L42_PAGE_10 + 0x01)
48 #define CS42L42_DEVID_CD (CS42L42_PAGE_10 + 0x02)
49 #define CS42L42_DEVID_E (CS42L42_PAGE_10 + 0x03)
50 #define CS42L42_FABID (CS42L42_PAGE_10 + 0x04)
51 #define CS42L42_REVID (CS42L42_PAGE_10 + 0x05)
52 #define CS42L42_FRZ_CTL (CS42L42_PAGE_10 + 0x06)
54 #define CS42L42_SRC_CTL (CS42L42_PAGE_10 + 0x07)
58 #define CS42L42_MCLK_STATUS (CS42L42_PAGE_10 + 0x08)
60 #define CS42L42_MCLK_CTL (CS42L42_PAGE_10 + 0x09)
64 #define CS42L42_SFTRAMP_RATE (CS42L42_PAGE_10 + 0x0A)
65 #define CS42L42_I2C_DEBOUNCE (CS42L42_PAGE_10 + 0x0E)
66 #define CS42L42_I2C_STRETCH (CS42L42_PAGE_10 + 0x0F)
67 #define CS42L42_I2C_TIMEOUT (CS42L42_PAGE_10 + 0x10)
69 /* Page 0x11 Power and Headset Detect Registers */
70 #define CS42L42_PWR_CTL1 (CS42L42_PAGE_11 + 0x01)
83 #define CS42L42_PDN_ALL_SHIFT 0
86 #define CS42L42_PWR_CTL2 (CS42L42_PAGE_11 + 0x02)
87 #define CS42L42_ADC_SRC_PDNB_SHIFT 0
98 #define CS42L42_PWR_CTL3 (CS42L42_PAGE_11 + 0x03)
109 #define CS42L42_RSENSE_CTL1 (CS42L42_PAGE_11 + 0x04)
110 #define CS42L42_RS_TRIM_R_SHIFT 0
126 #define CS42L42_RSENSE_CTL2 (CS42L42_PAGE_11 + 0x05)
130 #define CS42L42_OSC_SWITCH (CS42L42_PAGE_11 + 0x07)
131 #define CS42L42_SCLK_PRESENT_SHIFT 0
134 #define CS42L42_OSC_SWITCH_STATUS (CS42L42_PAGE_11 + 0x09)
135 #define CS42L42_OSC_SW_SEL_STAT_SHIFT 0
140 #define CS42L42_RSENSE_CTL3 (CS42L42_PAGE_11 + 0x12)
141 #define CS42L42_RS_RISE_DBNCE_TIME_SHIFT 0
154 #define CS42L42_TSENSE_CTL (CS42L42_PAGE_11 + 0x13)
155 #define CS42L42_TS_RISE_DBNCE_TIME_SHIFT 0
165 #define CS42L42_TSRS_INT_DISABLE (CS42L42_PAGE_11 + 0x14)
166 #define CS42L42_D_RS_PLUG_DBNC_SHIFT 0
175 #define CS42L42_TRSENSE_STATUS (CS42L42_PAGE_11 + 0x15)
176 #define CS42L42_RS_PLUG_DBNC_SHIFT 0
185 #define CS42L42_HSDET_CTL1 (CS42L42_PAGE_11 + 0x1F)
186 #define CS42L42_HSDET_COMP1_LVL_SHIFT 0
191 #define CS42L42_HSDET_CTL2 (CS42L42_PAGE_11 + 0x20)
192 #define CS42L42_HSDET_AUTO_TIME_SHIFT 0
201 #define CS42L42_HS_SWITCH_CTL (CS42L42_PAGE_11 + 0x21)
202 #define CS42L42_SW_GNDHS_HS4_SHIFT 0
219 #define CS42L42_HS_DET_STATUS (CS42L42_PAGE_11 + 0x24)
220 #define CS42L42_HSDET_TYPE_SHIFT 0
226 #define CS42L42_PLUG_CTIA 0
231 #define CS42L42_HS_CLAMP_DISABLE (CS42L42_PAGE_11 + 0x29)
232 #define CS42L42_HS_CLAMP_DISABLE_SHIFT 0
235 /* Page 0x12 Clocking Registers */
236 #define CS42L42_MCLK_SRC_SEL (CS42L42_PAGE_12 + 0x01)
239 #define CS42L42_MCLK_SRC_SEL_SHIFT 0
242 #define CS42L42_SPDIF_CLK_CFG (CS42L42_PAGE_12 + 0x02)
243 #define CS42L42_FSYNC_PW_LOWER (CS42L42_PAGE_12 + 0x03)
245 #define CS42L42_FSYNC_PW_UPPER (CS42L42_PAGE_12 + 0x04)
246 #define CS42L42_FSYNC_PULSE_WIDTH_SHIFT 0
247 #define CS42L42_FSYNC_PULSE_WIDTH_MASK (0xff << \
250 #define CS42L42_FSYNC_P_LOWER (CS42L42_PAGE_12 + 0x05)
252 #define CS42L42_FSYNC_P_UPPER (CS42L42_PAGE_12 + 0x06)
253 #define CS42L42_FSYNC_PERIOD_SHIFT 0
254 #define CS42L42_FSYNC_PERIOD_MASK (0xff << CS42L42_FSYNC_PERIOD_SHIFT)
256 #define CS42L42_ASP_CLK_CFG (CS42L42_PAGE_12 + 0x07)
259 #define CS42L42_ASP_MASTER_MODE 0x01
260 #define CS42L42_ASP_SLAVE_MODE 0x00
266 #define CS42L42_ASP_LCPOL_SHIFT 0
270 #define CS42L42_ASP_FRM_CFG (CS42L42_PAGE_12 + 0x08)
275 #define CS42L42_ASP_FSD_SHIFT 0
282 #define CS42L42_FS_RATE_EN (CS42L42_PAGE_12 + 0x09)
283 #define CS42L42_FS_EN_SHIFT 0
284 #define CS42L42_FS_EN_MASK (0xf << CS42L42_FS_EN_SHIFT)
285 #define CS42L42_FS_EN_IASRC_96K 0x1
286 #define CS42L42_FS_EN_OASRC_96K 0x2
288 #define CS42L42_IN_ASRC_CLK (CS42L42_PAGE_12 + 0x0A)
289 #define CS42L42_CLK_IASRC_SEL_SHIFT 0
293 #define CS42L42_OUT_ASRC_CLK (CS42L42_PAGE_12 + 0x0B)
294 #define CS42L42_CLK_OASRC_SEL_SHIFT 0
298 #define CS42L42_PLL_DIV_CFG1 (CS42L42_PAGE_12 + 0x0C)
299 #define CS42L42_SCLK_PREDIV_SHIFT 0
302 /* Page 0x13 Interrupt Registers */
304 #define CS42L42_ADC_OVFL_STATUS (CS42L42_PAGE_13 + 0x01)
305 #define CS42L42_MIXER_STATUS (CS42L42_PAGE_13 + 0x02)
306 #define CS42L42_SRC_STATUS (CS42L42_PAGE_13 + 0x03)
307 #define CS42L42_ASP_RX_STATUS (CS42L42_PAGE_13 + 0x04)
308 #define CS42L42_ASP_TX_STATUS (CS42L42_PAGE_13 + 0x05)
309 #define CS42L42_CODEC_STATUS (CS42L42_PAGE_13 + 0x08)
310 #define CS42L42_DET_INT_STATUS1 (CS42L42_PAGE_13 + 0x09)
311 #define CS42L42_DET_INT_STATUS2 (CS42L42_PAGE_13 + 0x0A)
312 #define CS42L42_SRCPL_INT_STATUS (CS42L42_PAGE_13 + 0x0B)
313 #define CS42L42_VPMON_STATUS (CS42L42_PAGE_13 + 0x0D)
314 #define CS42L42_PLL_LOCK_STATUS (CS42L42_PAGE_13 + 0x0E)
315 #define CS42L42_TSRS_PLUG_STATUS (CS42L42_PAGE_13 + 0x0F)
317 #define CS42L42_ADC_OVFL_INT_MASK (CS42L42_PAGE_13 + 0x16)
318 #define CS42L42_ADC_OVFL_SHIFT 0
322 #define CS42L42_MIXER_INT_MASK (CS42L42_PAGE_13 + 0x17)
323 #define CS42L42_MIX_CHB_OVFL_SHIFT 0
336 #define CS42L42_SRC_INT_MASK (CS42L42_PAGE_13 + 0x18)
337 #define CS42L42_SRC_ILK_SHIFT 0
350 #define CS42L42_ASP_RX_INT_MASK (CS42L42_PAGE_13 + 0x19)
351 #define CS42L42_ASPRX_NOLRCK_SHIFT 0
367 #define CS42L42_ASP_TX_INT_MASK (CS42L42_PAGE_13 + 0x1A)
368 #define CS42L42_ASPTX_NOLRCK_SHIFT 0
381 #define CS42L42_CODEC_INT_MASK (CS42L42_PAGE_13 + 0x1B)
382 #define CS42L42_PDN_DONE_SHIFT 0
389 #define CS42L42_SRCPL_INT_MASK (CS42L42_PAGE_13 + 0x1C)
390 #define CS42L42_SRCPL_ADC_LK_SHIFT 0
403 #define CS42L42_VPMON_INT_MASK (CS42L42_PAGE_13 + 0x1E)
404 #define CS42L42_VPMON_SHIFT 0
408 #define CS42L42_PLL_LOCK_INT_MASK (CS42L42_PAGE_13 + 0x1F)
409 #define CS42L42_PLL_LOCK_SHIFT 0
413 #define CS42L42_TSRS_PLUG_INT_MASK (CS42L42_PAGE_13 + 0x20)
414 #define CS42L42_RS_PLUG_SHIFT 0
427 #define CS42L42_TS_UNPLUG 0
430 /* Page 0x15 Fractional-N PLL Registers */
431 #define CS42L42_PLL_CTL1 (CS42L42_PAGE_15 + 0x01)
432 #define CS42L42_PLL_START_SHIFT 0
435 #define CS42L42_PLL_DIV_FRAC0 (CS42L42_PAGE_15 + 0x02)
436 #define CS42L42_PLL_DIV_FRAC_SHIFT 0
437 #define CS42L42_PLL_DIV_FRAC_MASK (0xff << CS42L42_PLL_DIV_FRAC_SHIFT)
439 #define CS42L42_PLL_DIV_FRAC1 (CS42L42_PAGE_15 + 0x03)
440 #define CS42L42_PLL_DIV_FRAC2 (CS42L42_PAGE_15 + 0x04)
442 #define CS42L42_PLL_DIV_INT (CS42L42_PAGE_15 + 0x05)
443 #define CS42L42_PLL_DIV_INT_SHIFT 0
444 #define CS42L42_PLL_DIV_INT_MASK (0xff << CS42L42_PLL_DIV_INT_SHIFT)
446 #define CS42L42_PLL_CTL3 (CS42L42_PAGE_15 + 0x08)
447 #define CS42L42_PLL_DIVOUT_SHIFT 0
448 #define CS42L42_PLL_DIVOUT_MASK (0xff << CS42L42_PLL_DIVOUT_SHIFT)
450 #define CS42L42_PLL_CAL_RATIO (CS42L42_PAGE_15 + 0x0A)
451 #define CS42L42_PLL_CAL_RATIO_SHIFT 0
452 #define CS42L42_PLL_CAL_RATIO_MASK (0xff << CS42L42_PLL_CAL_RATIO_SHIFT)
454 #define CS42L42_PLL_CTL4 (CS42L42_PAGE_15 + 0x1B)
455 #define CS42L42_PLL_MODE_SHIFT 0
458 /* Page 0x19 HP Load Detect Registers */
459 #define CS42L42_LOAD_DET_RCSTAT (CS42L42_PAGE_19 + 0x25)
460 #define CS42L42_RLA_STAT_SHIFT 0
462 #define CS42L42_RLA_STAT_15_OHM 0
464 #define CS42L42_LOAD_DET_DONE (CS42L42_PAGE_19 + 0x26)
465 #define CS42L42_HPLOAD_DET_DONE_SHIFT 0
468 #define CS42L42_LOAD_DET_EN (CS42L42_PAGE_19 + 0x27)
469 #define CS42L42_HP_LD_EN_SHIFT 0
472 /* Page 0x1B Headset Interface Registers */
473 #define CS42L42_HSBIAS_SC_AUTOCTL (CS42L42_PAGE_1B + 0x70)
474 #define CS42L42_HSBIAS_SENSE_TRIP_SHIFT 0
487 #define CS42L42_WAKE_CTL (CS42L42_PAGE_1B + 0x71)
488 #define CS42L42_WAKEB_CLEAR_SHIFT 0
497 #define CS42L42_ADC_DISABLE_MUTE (CS42L42_PAGE_1B + 0x72)
502 #define CS42L42_TIPSENSE_CTL (CS42L42_PAGE_1B + 0x73)
503 #define CS42L42_TIP_SENSE_DEBOUNCE_SHIFT 0
513 #define CS42L42_MISC_DET_CTL (CS42L42_PAGE_1B + 0x74)
514 #define CS42L42_PDN_MIC_LVL_DET_SHIFT 0
521 #define CS42L42_MIC_DET_CTL1 (CS42L42_PAGE_1B + 0x75)
522 #define CS42L42_HS_DET_LEVEL_SHIFT 0
523 #define CS42L42_HS_DET_LEVEL_MASK (0x3F << CS42L42_HS_DET_LEVEL_SHIFT)
529 #define CS42L42_MIC_DET_CTL2 (CS42L42_PAGE_1B + 0x76)
531 #define CS42L42_DEBOUNCE_TIME_MASK (0x07 << CS42L42_DEBOUNCE_TIME_SHIFT)
533 #define CS42L42_DET_STATUS1 (CS42L42_PAGE_1B + 0x77)
539 #define CS42L42_DET_STATUS2 (CS42L42_PAGE_1B + 0x78)
540 #define CS42L42_SHORT_TRUE_SHIFT 0
545 #define CS42L42_DET_INT1_MASK (CS42L42_PAGE_1B + 0x79)
556 #define CS42L42_DET_INT2_MASK (CS42L42_PAGE_1B + 0x7A)
557 #define CS42L42_M_SHORT_DET_SHIFT 0
578 /* Page 0x1C Headset Bias Registers */
579 #define CS42L42_HS_BIAS_CTL (CS42L42_PAGE_1C + 0x03)
580 #define CS42L42_HSBIAS_RAMP_SHIFT 0
587 /* Page 0x1D ADC Registers */
588 #define CS42L42_ADC_CTL (CS42L42_PAGE_1D + 0x01)
592 #define CS42L42_ADC_DIG_BOOST_SHIFT 0
594 #define CS42L42_ADC_VOLUME (CS42L42_PAGE_1D + 0x03)
595 #define CS42L42_ADC_VOL_SHIFT 0
597 #define CS42L42_ADC_WNF_HPF_CTL (CS42L42_PAGE_1D + 0x04)
601 #define CS42L42_ADC_HPF_EN_SHIFT 0
603 /* Page 0x1F DAC Registers */
604 #define CS42L42_DAC_CTL1 (CS42L42_PAGE_1F + 0x01)
606 #define CS42L42_DACA_INV_SHIFT 0
608 #define CS42L42_DAC_CTL2 (CS42L42_PAGE_1F + 0x06)
617 #define CS42L42_DAC_MON_EN_SHIFT 0
620 /* Page 0x20 HP CTL Registers */
621 #define CS42L42_HP_CTL (CS42L42_PAGE_20 + 0x01)
629 /* Page 0x21 Class H Registers */
630 #define CS42L42_CLASSH_CTL (CS42L42_PAGE_21 + 0x01)
632 /* Page 0x23 Mixer Volume Registers */
633 #define CS42L42_MIXER_CHA_VOL (CS42L42_PAGE_23 + 0x01)
634 #define CS42L42_MIXER_ADC_VOL (CS42L42_PAGE_23 + 0x02)
636 #define CS42L42_MIXER_CHB_VOL (CS42L42_PAGE_23 + 0x03)
637 #define CS42L42_MIXER_CH_VOL_SHIFT 0
638 #define CS42L42_MIXER_CH_VOL_MASK (0x3f << CS42L42_MIXER_CH_VOL_SHIFT)
640 /* Page 0x24 EQ Registers */
641 #define CS42L42_EQ_COEF_IN0 (CS42L42_PAGE_24 + 0x01)
642 #define CS42L42_EQ_COEF_IN1 (CS42L42_PAGE_24 + 0x02)
643 #define CS42L42_EQ_COEF_IN2 (CS42L42_PAGE_24 + 0x03)
644 #define CS42L42_EQ_COEF_IN3 (CS42L42_PAGE_24 + 0x04)
645 #define CS42L42_EQ_COEF_RW (CS42L42_PAGE_24 + 0x06)
646 #define CS42L42_EQ_COEF_OUT0 (CS42L42_PAGE_24 + 0x07)
647 #define CS42L42_EQ_COEF_OUT1 (CS42L42_PAGE_24 + 0x08)
648 #define CS42L42_EQ_COEF_OUT2 (CS42L42_PAGE_24 + 0x09)
649 #define CS42L42_EQ_COEF_OUT3 (CS42L42_PAGE_24 + 0x0A)
650 #define CS42L42_EQ_INIT_STAT (CS42L42_PAGE_24 + 0x0B)
651 #define CS42L42_EQ_START_FILT (CS42L42_PAGE_24 + 0x0C)
652 #define CS42L42_EQ_MUTE_CTL (CS42L42_PAGE_24 + 0x0E)
654 /* Page 0x25 Audio Port Registers */
655 #define CS42L42_SP_RX_CH_SEL (CS42L42_PAGE_25 + 0x01)
659 #define CS42L42_SP_RX_ISOC_CTL (CS42L42_PAGE_25 + 0x02)
666 #define CS42L42_SP_RX_ISOC_MODE_SHIFT 0
669 #define CS42L42_SP_RX_FS (CS42L42_PAGE_25 + 0x03)
670 #define CS42l42_SPDIF_CH_SEL (CS42L42_PAGE_25 + 0x04)
671 #define CS42L42_SP_TX_ISOC_CTL (CS42L42_PAGE_25 + 0x05)
672 #define CS42L42_SP_TX_FS (CS42L42_PAGE_25 + 0x06)
673 #define CS42L42_SPDIF_SW_CTL1 (CS42L42_PAGE_25 + 0x07)
675 /* Page 0x26 SRC Registers */
676 #define CS42L42_SRC_SDIN_FS (CS42L42_PAGE_26 + 0x01)
677 #define CS42L42_SRC_SDIN_FS_SHIFT 0
678 #define CS42L42_SRC_SDIN_FS_MASK (0x1f << CS42L42_SRC_SDIN_FS_SHIFT)
680 #define CS42L42_SRC_SDOUT_FS (CS42L42_PAGE_26 + 0x09)
682 /* Page 0x28 S/PDIF Registers */
683 #define CS42L42_SPDIF_CTL1 (CS42L42_PAGE_28 + 0x01)
684 #define CS42L42_SPDIF_CTL2 (CS42L42_PAGE_28 + 0x02)
685 #define CS42L42_SPDIF_CTL3 (CS42L42_PAGE_28 + 0x03)
686 #define CS42L42_SPDIF_CTL4 (CS42L42_PAGE_28 + 0x04)
688 /* Page 0x29 Serial Port TX Registers */
689 #define CS42L42_ASP_TX_SZ_EN (CS42L42_PAGE_29 + 0x01)
690 #define CS42L42_ASP_TX_EN_SHIFT 0
691 #define CS42L42_ASP_TX_CH_EN (CS42L42_PAGE_29 + 0x02)
693 #define CS42L42_ASP_TX0_CH1_SHIFT 0
695 #define CS42L42_ASP_TX_CH_AP_RES (CS42L42_PAGE_29 + 0x03)
702 #define CS42L42_ASP_TX_CH1_RES_SHIFT 0
704 #define CS42L42_ASP_TX_CH1_BIT_MSB (CS42L42_PAGE_29 + 0x04)
705 #define CS42L42_ASP_TX_CH1_BIT_LSB (CS42L42_PAGE_29 + 0x05)
706 #define CS42L42_ASP_TX_HIZ_DLY_CFG (CS42L42_PAGE_29 + 0x06)
707 #define CS42L42_ASP_TX_CH2_BIT_MSB (CS42L42_PAGE_29 + 0x0A)
708 #define CS42L42_ASP_TX_CH2_BIT_LSB (CS42L42_PAGE_29 + 0x0B)
710 /* Page 0x2A Serial Port RX Registers */
711 #define CS42L42_ASP_RX_DAI0_EN (CS42L42_PAGE_2A + 0x01)
713 #define CS42L42_ASP_RX0_CH_EN_MASK (0xf << CS42L42_ASP_RX0_CH_EN_SHIFT)
719 #define CS42L42_ASP_RX_DAI0_CH1_AP_RES (CS42L42_PAGE_2A + 0x02)
720 #define CS42L42_ASP_RX_DAI0_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x03)
721 #define CS42L42_ASP_RX_DAI0_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x04)
722 #define CS42L42_ASP_RX_DAI0_CH2_AP_RES (CS42L42_PAGE_2A + 0x05)
723 #define CS42L42_ASP_RX_DAI0_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x06)
724 #define CS42L42_ASP_RX_DAI0_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x07)
725 #define CS42L42_ASP_RX_DAI0_CH3_AP_RES (CS42L42_PAGE_2A + 0x08)
726 #define CS42L42_ASP_RX_DAI0_CH3_BIT_MSB (CS42L42_PAGE_2A + 0x09)
727 #define CS42L42_ASP_RX_DAI0_CH3_BIT_LSB (CS42L42_PAGE_2A + 0x0A)
728 #define CS42L42_ASP_RX_DAI0_CH4_AP_RES (CS42L42_PAGE_2A + 0x0B)
729 #define CS42L42_ASP_RX_DAI0_CH4_BIT_MSB (CS42L42_PAGE_2A + 0x0C)
730 #define CS42L42_ASP_RX_DAI0_CH4_BIT_LSB (CS42L42_PAGE_2A + 0x0D)
731 #define CS42L42_ASP_RX_DAI1_CH1_AP_RES (CS42L42_PAGE_2A + 0x0E)
732 #define CS42L42_ASP_RX_DAI1_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x0F)
733 #define CS42L42_ASP_RX_DAI1_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x10)
734 #define CS42L42_ASP_RX_DAI1_CH2_AP_RES (CS42L42_PAGE_2A + 0x11)
735 #define CS42L42_ASP_RX_DAI1_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x12)
736 #define CS42L42_ASP_RX_DAI1_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x13)
740 #define CS42L42_ASP_RX_CH_AP_LOW 0
742 #define CS42L42_ASP_RX_CH_RES_SHIFT 0
746 #define CS42L42_ASP_RX_CH_BIT_ST_SHIFT 0
747 #define CS42L42_ASP_RX_CH_BIT_ST_MASK (0xff << CS42L42_ASP_RX_CH_BIT_ST_SHIFT)
749 /* Page 0x30 ID Registers */
750 #define CS42L42_SUB_REVID (CS42L42_PAGE_30 + 0x14)
751 #define CS42L42_MAX_REGISTER (CS42L42_PAGE_30 + 0x14)
754 #define CS42L42_FRAC0_VAL(val) ((val) & 0x0000ff)
755 #define CS42L42_FRAC1_VAL(val) (((val) & 0x00ff00) >> 8)
756 #define CS42L42_FRAC2_VAL(val) (((val) & 0xff0000) >> 16)