79 #define CM_REG_FUNCTRL1		0x04  macro
816 	val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);  in snd_cmipci_pcm_prepare()
824 	snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);  in snd_cmipci_pcm_prepare()
1241 			snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);  in setup_spdif_playback()
1257 		snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);  in setup_spdif_playback()
1327 		val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);  in snd_cmipci_silence_hack()
1330 		snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);  in snd_cmipci_silence_hack()
1386 	snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);  in snd_cmipci_capture_spdif_prepare()
1408 	snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);  in snd_cmipci_capture_spdif_hw_free()
2411 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2412 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2417 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2423 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2475 				snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);  in snd_cmipci_spdout_enable_put()
2478 				snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);  in snd_cmipci_spdout_enable_put()
2881 	snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);  in snd_cmipci_create_gameport()
2894 		snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);  in snd_cmipci_free_gameport()
2912 	snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);  in snd_cmipci_free()
3054 	snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);  in snd_cmipci_create()
3068 	snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);  in snd_cmipci_create()
3138 			snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);  in snd_cmipci_create()
3143 				snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,  in snd_cmipci_create()
3206 		snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);  in snd_cmipci_create()
3269 	CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,