Lines Matching +full:0 +full:x01400000
12 #define FORMER_REG_SYNC_STATUS 0x0000801c0000ull
14 #define FORMER_REG_FETCH_PCM_FRAMES 0x0000801c0000ull
15 #define FORMER_REG_CLOCK_CONFIG 0x0000801c0004ull
24 { 32000, 0x00000002, }, in parse_clock_bits()
25 { 44100, 0x00000000, }, in parse_clock_bits()
26 { 48000, 0x00000006, }, in parse_clock_bits()
27 { 64000, 0x0000000a, }, in parse_clock_bits()
28 { 88200, 0x00000008, }, in parse_clock_bits()
29 { 96000, 0x0000000e, }, in parse_clock_bits()
30 { 128000, 0x00000012, }, in parse_clock_bits()
31 { 176400, 0x00000010, }, in parse_clock_bits()
32 { 192000, 0x00000016, }, in parse_clock_bits()
38 { SND_FF_CLOCK_SRC_ADAT1, 0x00000000, }, in parse_clock_bits()
39 { SND_FF_CLOCK_SRC_ADAT2, 0x00000400, }, in parse_clock_bits()
40 { SND_FF_CLOCK_SRC_SPDIF, 0x00000c00, }, in parse_clock_bits()
41 { SND_FF_CLOCK_SRC_WORD, 0x00001000, }, in parse_clock_bits()
42 { SND_FF_CLOCK_SRC_LTC, 0x00001800, }, in parse_clock_bits()
46 for (i = 0; i < ARRAY_SIZE(rate_entries); ++i) { in parse_clock_bits()
48 if ((data & 0x0000001e) == rate_entry->mask) { in parse_clock_bits()
56 if (data & 0x00000001) { in parse_clock_bits()
59 for (i = 0; i < ARRAY_SIZE(clk_entries); ++i) { in parse_clock_bits()
61 if ((data & 0x00001c00) == clk_entry->mask) { in parse_clock_bits()
70 return 0; in parse_clock_bits()
81 FORMER_REG_CLOCK_CONFIG, ®, sizeof(reg), 0); in former_get_clock()
82 if (err < 0) in former_get_clock()
96 count = 0; in former_switch_fetching_mode()
97 for (i = 0; i < SND_FF_STREAM_MODE_COUNT; ++i) in former_switch_fetching_mode()
112 for (i = 0; i < count; ++i) in former_switch_fetching_mode()
113 reg[i] = cpu_to_le32(0x00000001); in former_switch_fetching_mode()
118 sizeof(__le32) * count, 0); in former_switch_fetching_mode()
133 FORMER_REG_CLOCK_CONFIG, ®, sizeof(reg), 0); in dump_clock_config()
134 if (err < 0) in dump_clock_config()
139 (data & 0x00000020) ? "Professional" : "Consumer", in dump_clock_config()
140 (data & 0x00000040) ? "on" : "off"); in dump_clock_config()
143 (data & 0x00000100) ? "S/PDIF" : "ADAT"); in dump_clock_config()
146 (data & 0x00002000) ? "on" : "off"); in dump_clock_config()
149 (data & 0x00000200) ? "Optical" : "Coaxial"); in dump_clock_config()
152 if (err < 0) in dump_clock_config()
168 { "WDClk", 0x40000000, 0x20000000, }, in dump_sync_status()
169 { "S/PDIF", 0x00080000, 0x00040000, }, in dump_sync_status()
170 { "ADAT1", 0x00000400, 0x00001000, }, in dump_sync_status()
171 { "ADAT2", 0x00000800, 0x00002000, }, in dump_sync_status()
177 { "ADAT1", 0x00000000, }, in dump_sync_status()
178 { "ADAT2", 0x00400000, }, in dump_sync_status()
179 { "S/PDIF", 0x00c00000, }, in dump_sync_status()
180 { "WDclk", 0x01000000, }, in dump_sync_status()
181 { "TCO", 0x01400000, }, in dump_sync_status()
187 { 32000, 0x02000000, }, in dump_sync_status()
188 { 44100, 0x04000000, }, in dump_sync_status()
189 { 48000, 0x06000000, }, in dump_sync_status()
190 { 64000, 0x08000000, }, in dump_sync_status()
191 { 88200, 0x0a000000, }, in dump_sync_status()
192 { 96000, 0x0c000000, }, in dump_sync_status()
193 { 128000, 0x0e000000, }, in dump_sync_status()
194 { 176400, 0x10000000, }, in dump_sync_status()
195 { 192000, 0x12000000, }, in dump_sync_status()
203 FORMER_REG_SYNC_STATUS, reg, sizeof(reg), 0); in dump_sync_status()
204 if (err < 0) in dump_sync_status()
206 data[0] = le32_to_cpu(reg[0]); in dump_sync_status()
211 for (i = 0; i < ARRAY_SIZE(clk_entries); ++i) { in dump_sync_status()
215 if (data[0] & clk_entry->locked_mask) { in dump_sync_status()
216 if (data[0] & clk_entry->synced_mask) in dump_sync_status()
229 if (data[1] & 0x00000001) { in dump_sync_status()
235 for (i = 0; i < ARRAY_SIZE(referred_entries); ++i) { in dump_sync_status()
237 if ((data[0] & 0x1e0000) == referred_entry->mask) { in dump_sync_status()
245 for (i = 0; i < ARRAY_SIZE(rate_entries); ++i) { in dump_sync_status()
247 if ((data[0] & 0x1e000000) == rate_entry->mask) { in dump_sync_status()
253 rate = 0; in dump_sync_status()
276 if (len <= 0) in former_fill_midi_msg()
280 for (i = len - 1; i >= 0; --i) in former_fill_midi_msg()
287 #define FF800_STF 0x0000fc88f000
288 #define FF800_RX_PACKET_FORMAT 0x0000fc88f004
289 #define FF800_ALLOC_TX_STREAM 0x0000fc88f008
290 #define FF800_ISOC_COMM_START 0x0000fc88f00c
291 #define FF800_TX_S800_FLAG 0x00000800
292 #define FF800_ISOC_COMM_STOP 0x0000fc88f010
294 #define FF800_TX_PACKET_ISOC_CH 0x0000801c0008
305 FF800_ALLOC_TX_STREAM, ®, sizeof(reg), 0); in allocate_tx_resources()
306 if (err < 0) in allocate_tx_resources()
310 count = 0; in allocate_tx_resources()
314 FF800_TX_PACKET_ISOC_CH, ®, sizeof(reg), 0); in allocate_tx_resources()
315 if (err < 0) in allocate_tx_resources()
319 if (data != 0xffffffff) { in allocate_tx_resources()
334 return 0; in allocate_tx_resources()
345 FF800_STF, ®, sizeof(reg), 0); in ff800_allocate_resources()
346 if (err < 0) in ff800_allocate_resources()
358 if (err < 0) in ff800_allocate_resources()
368 FF800_RX_PACKET_FORMAT, ®, sizeof(reg), 0); in ff800_allocate_resources()
369 if (err < 0) in ff800_allocate_resources()
382 if (err < 0) in ff800_begin_session()
386 reg = cpu_to_le32(0x80000000); in ff800_begin_session()
391 FF800_ISOC_COMM_START, ®, sizeof(reg), 0); in ff800_begin_session()
398 reg = cpu_to_le32(0x80000000); in ff800_finish_session()
400 FF800_ISOC_COMM_STOP, ®, sizeof(reg), 0); in ff800_finish_session()
412 for (i = 0; i < length / 4; i++) { in ff800_handle_midi_msg()
413 u8 byte = le32_to_cpu(buf[i]) & 0xff; in ff800_handle_midi_msg()
416 substream = READ_ONCE(ff->tx_midi_substreams[0]); in ff800_handle_midi_msg()
433 #define FF400_STF 0x000080100500ull
434 #define FF400_RX_PACKET_FORMAT 0x000080100504ull
435 #define FF400_ISOC_COMM_START 0x000080100508ull
436 #define FF400_TX_PACKET_FORMAT 0x00008010050cull
437 #define FF400_ISOC_COMM_STOP 0x000080100510ull
440 // we can allocate between 0 and 7 channel.
449 for (i = 0; i < CIP_SFC_COUNT; i++) { in ff400_allocate_resources()
459 FF400_STF, ®, sizeof(reg), 0); in ff400_allocate_resources()
460 if (err < 0) in ff400_allocate_resources()
466 if (err < 0) in ff400_allocate_resources()
470 ff->tx_resources.channels_mask = 0x00000000000000ffuLL; in ff400_allocate_resources()
474 if (err < 0) in ff400_allocate_resources()
478 ff->rx_resources.channels_mask = 0x00000000000000ffuLL; in ff400_allocate_resources()
482 if (err < 0) in ff400_allocate_resources()
496 if (err < 0) in ff400_begin_session()
500 if (err < 0) in ff400_begin_session()
509 FF400_RX_PACKET_FORMAT, ®, sizeof(reg), 0); in ff400_begin_session()
510 if (err < 0) in ff400_begin_session()
515 // TODO: investigate the purpose of this 0x80. in ff400_begin_session()
516 reg = cpu_to_le32((0x80 << 24) | in ff400_begin_session()
520 FF400_TX_PACKET_FORMAT, ®, sizeof(reg), 0); in ff400_begin_session()
521 if (err < 0) in ff400_begin_session()
525 reg = cpu_to_le32(0x00000001); in ff400_begin_session()
527 FF400_ISOC_COMM_START, ®, sizeof(reg), 0); in ff400_begin_session()
534 reg = cpu_to_le32(0x80000000); in ff400_finish_session()
536 FF400_ISOC_COMM_STOP, ®, sizeof(reg), 0); in ff400_finish_session()
540 // flag in quadlet register (little endian) at 0x'0000'801'0051c. Drivers can
544 // - 0x04000000: 0x'....'....'0000'0000
545 // - 0x08000000: 0x'....'....'0000'0080
546 // - 0x10000000: 0x'....'....'0000'0100
547 // - 0x20000000: 0x'....'....'0000'0180
551 // - 0x01000000: suppress transmission
552 // - 0x02000000: suppress transmission
563 for (i = 0; i < length / 4; i++) { in ff400_handle_midi_msg()
575 index = (quad >> 8) & 0xff; in ff400_handle_midi_msg()
576 if (index > 0) { in ff400_handle_midi_msg()
577 substream = READ_ONCE(ff->tx_midi_substreams[0]); in ff400_handle_midi_msg()
579 byte = quad & 0xff; in ff400_handle_midi_msg()
585 index = (quad >> 24) & 0xff; in ff400_handle_midi_msg()
586 if (index > 0) { in ff400_handle_midi_msg()
589 byte = (quad >> 16) & 0xff; in ff400_handle_midi_msg()