Lines Matching full:cpu1
23 * CPU1 after the IPI-induced memory barrier:
25 * CPU0 CPU1
39 * The write to y and load from x by CPU1 are unordered by the hardware,
47 * before the IPI-induced memory barrier on CPU1.
57 * order to enforce the guarantee that any writes occurring on CPU1 before
61 * CPU0 CPU1
81 * after the IPI-induced memory barrier on CPU1.
85 * CPU0 CPU1
103 * and Thread B). Thread A runs on CPU0, Thread B runs on CPU1.
105 * CPU0 CPU1
119 * CPU0 CPU1