Lines Matching full:1280
86 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
95 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
104 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
114 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
123 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
466 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
474 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
481 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
488 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
495 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
503 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
511 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
518 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
525 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
532 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
540 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
548 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
556 V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \
565 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
573 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
581 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
589 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \