Lines Matching +full:protect +full:- +full:exec

1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
13 #define IOMMU_FAULT_PERM_EXEC	(1 << 2) /* exec */
60  * struct iommu_fault_unrecoverable - Unrecoverable fault data
82  * struct iommu_fault_page_request - Page Request data
92  * @private_data: device-specific private information
108  * struct iommu_fault - Generic fault data
126  * enum iommu_page_response_code - Return status of fault handlers
141  * struct iommu_page_response - Generic page response information
163 	IOMMU_INV_GRANU_DOMAIN,	/* domain-selective invalidation */
164 	IOMMU_INV_GRANU_PASID,	/* PASID-selective invalidation */
165 	IOMMU_INV_GRANU_ADDR,	/* page-selective invalidation */
170  * struct iommu_inv_addr_info - Address Selective Invalidation Structure
172  * @flags: indicates the granularity of the address-selective invalidation
173  * - If the PASID bit is set, the @pasid field is populated and the invalidation
176  * - If ARCHID bit is set, @archid is populated and the invalidation relates
179  * - Both PASID and ARCHID can be set as they may tag different caches.
180  * - If neither PASID or ARCHID is set, global addr invalidation applies.
181  * - The LEAF flag indicates whether only the leaf PTE caching needs to be
184  * @archid: architecture-specific ID
202  * struct iommu_inv_pasid_info - PASID Selective Invalidation Structure
204  * @flags: indicates the granularity of the PASID-selective invalidation
205  * - If the PASID bit is set, the @pasid field is populated and the invalidation
208  * - If the ARCHID bit is set, the @archid is populated and the invalidation
211  * - Both PASID and ARCHID can be set as they may tag different caches.
212  * - At least one of PASID or ARCHID must be set.
214  * @archid: architecture-specific ID
225  * struct iommu_cache_invalidate_info - First level/stage invalidation
238  * +--------------+---------------+---------------+---------------+
243  * +--------------+---------------+---------------+---------------+
245  * +--------------+---------------+---------------+---------------+
247  * +--------------+---------------+---------------+---------------+
274  * struct iommu_gpasid_bind_data_vtd - Intel VT-d specific data on device and guest
277  * @flags:	VT-d PASID table entry attributes
287 #define IOMMU_SVA_VTD_GPASID_PCD	(1 << 2) /* page-level cache disable */
288 #define IOMMU_SVA_VTD_GPASID_PWT	(1 << 3) /* page-level write through */
290 #define IOMMU_SVA_VTD_GPASID_CD		(1 << 5) /* PASID-level cache disable */
291 #define IOMMU_SVA_VTD_GPASID_WPE	(1 << 6) /* Write protect enable */
304  * struct iommu_gpasid_bind_data - Information about device and guest PASID binding
314  * @vtd:	Intel VT-d specific data
316  * Guest to host PASID mapping can be an identity or non-identity, where guest
317  * has its own PASID space. For non-identify mapping, guest to host PASID lookup