Lines Matching full:layout
46 * format and data layout of the buffer, and should be the only way to describe
49 * Having multiple fourcc:modifier pairs which describe the same layout should
61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must
243 * then V), but the exact Linear layout is undefined.
382 * When adding a new token please document the layout with a code comment,
398 * In future cases where a generic layout is identified before merging with a
422 * Linear Layout
424 * Just plain linear layout. Note that this is different from no specifying any
435 * implicit, instead it means that the layout is linear. Whether modifiers are
444 * Intel X-tiling layout
446 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
447 * in row-major layout. Within the tile bytes are laid out row-major, with
451 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
454 * identify the layout in a simple way for i915-specific userspace, which
461 * Intel Y-tiling layout
463 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
464 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
469 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
472 * identify the layout in a simple way for i915-specific userspace, which
479 * Intel Yf-tiling layout
481 * This is a tiled layout using 4Kb tiles in row-major layout.
483 * are arranged in four groups (two wide, two high) with column-major layout.
574 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
575 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
596 * Vivante 4x4 tiling layout
598 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
599 * layout.
604 * Vivante 64x64 super-tiling layout
606 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
608 * major layout.
616 * Vivante 4x4 tiling layout for dual-pipe
618 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
620 * compared to the non-split tiled layout.
625 * Vivante 64x64 super-tiling layout for dual-pipe
627 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
629 * therefore halved compared to the non-split super-tiled layout.
636 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
643 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
646 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
663 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
680 * tables of all GPUs >= NV50. It affects the exact layout of bits
688 * since the modifier should define the layout of the associated
694 * kind and bit layout has changed at various points.
701 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
703 * page kind and block linear swizzles. This causes the layout of
707 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
708 * 1 = Desktop GPU and Tegra Xavier+ Layout
713 * 1 = ROP/3D, layout 1, exact compression format implied by Page
715 * 2 = ROP/3D, layout 2, exact compression format implied by Page
733 /* To grandfather in prior block linear format modifiers to the above layout,
749 * 16Bx2 Block Linear layout, used by Tegra K1 and later
805 * This is the primary layout that the V3D GPU can texture from (it
953 * AFBC sparse layout
974 * AFBC tiled layout
976 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
980 * When the tiled layout is used, the buffer size (in pixels) must be aligned
996 * Indicates that the buffer is allocated in a layout safe for front-buffer
1013 * The buffer layout is the same as for AFBC buffers without USM set, this only
1049 * scanline (SCAN layout) or rotated (ROT layout) access.
1051 * Layout Paging Tile Width Paging Tile Height
1058 * scanline (SCAN layout) or rotated (ROT layout) access.
1060 * Number of Components in Plane Layout Coding Unit Width Coding Unit Height
1115 * AFRC scanline memory layout.
1117 * Indicates if the buffer uses the scanline-optimised layout
1118 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
1119 * The memory layout is the same for all planes.
1162 * The first 8 bits of the mode defines the layout, then the following 8 bits
1163 * defines the options changing the layout.
1166 * combinations of layout and options.
1181 * Amlogic FBC Basic Layout
1183 * The basic layout is composed of:
1188 * This layout is transferrable between Amlogic SoCs supporting this modifier.
1193 * Amlogic FBC Scatter Memory layout
1196 * frames content to optimize memory access and layout.
1203 * Due to the nature of the layout, these buffers are not expected to
1212 /* Amlogic FBC Layout Options Bit Mask */
1221 * This mode reduces body layout to 3072 bytes per 64x32 superblock with
1222 * the basic layout and 3200 bytes per 64x32 superblock combined with
1223 * the scatter layout.
1230 * Memory layout: