Lines Matching full:ccs
494 * Intel color control surface (CCS) for render compression
498 * the CCS will be plane index 1.
500 * Each CCS tile matches a 1024x512 pixel area of the main surface.
501 * To match certain aspects of the 3D hardware the CCS is
503 * the CCS pitch must be specified in multiples of 128 bytes.
505 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
514 * Intel color control surfaces (CCS) for Gen-12 render compression.
516 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
517 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
518 * main surface. In other words, 4 bits in CCS map to a main surface cache
525 * Intel color control surfaces (CCS) for Gen-12 media compression
527 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
528 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
529 * main surface. In other words, 4 bits in CCS map to a main surface cache
531 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
533 * planes 2 and 3 for the respective CCS.
538 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
541 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
550 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line