Lines Matching +full:10 +full:a
4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
38 * fourcc code, a Format Modifier may optionally be provided, in order to
44 * Format modifiers are used in conjunction with a fourcc code, forming a
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must
62 * match only a single modifier. A modifier must not be a subset of layouts of
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
69 * a canonical pair needs to be defined and used by all drivers. Preferred
93 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ argument
128 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian…
129 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian…
130 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian…
131 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian…
138 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian…
139 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian…
140 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian…
141 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian…
156 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian…
157 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian…
158 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian…
159 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian…
161 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little …
162 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little …
163 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little …
164 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little …
166 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little …
167 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little …
168 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little …
169 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little …
175 #define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 littl…
176 #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 littl…
181 * [15:0] sign:exponent:mantissa 1:5:10
186 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 litt…
187 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 litt…
190 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
193 …DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:…
201 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian …
204 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. N…
210 … fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little end…
218 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 litt…
219 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12…
220 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 lit…
222 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 littl…
228 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
235 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
237 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
244 * These formats can only be used with a non-Linear modifier.
250 * 2 plane RGB + A
252 * index 1 = A plane, [7:0] A
254 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
255 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
256 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
257 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
258 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
259 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
260 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
261 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
285 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
286 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
288 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per …
292 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
293 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
295 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per …
312 * 16 bits per component, but only 10 bits are used and 6 bits are padded
313 * index 0: Y plane, [15:0] Y:x [10:6] little endian
314 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian
315 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian
320 * 16 bits per component, but only 10 bits are used and 6 bits are padded
321 * index 0: Y plane, [15:0] Y:x [10:6] little endian
322 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian
323 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian
351 * Format modifiers describe, typically, a re-ordering or modification
352 * of the data in a plane of an FB. This can be used to express tiled/
353 * swizzled formats, or compression, or a combination of the two.
355 * The upper 8 bits of the format modifier are a vendor-id as assigned
382 * When adding a new token please document the layout with a code comment,
390 * compatibility, in cases where a vendor-specific definition already exists and
391 * a generic name for it is desired, the common name is a purely symbolic alias
398 * In future cases where a generic layout is identified before merging with a
399 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
402 * apply to a single vendor.
415 * This modifier can be used as a sentinel to terminate the format modifiers
416 * list, or to initialize a variable with an invalid modifier. It might also be
427 * and so might actually result in a tiled framebuffer.
436 * used is out-of-band information carried in an API-specific way (e.g. in a
446 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
448 * a platform-dependent stride. On top of that the memory can apply
453 * cross-driver sharing. It exists since on a given platform it does uniquely
454 * identify the layout in a simple way for i915-specific userspace, which
463 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
465 * chunks column-major, with a platform-dependent height. On top of that the
471 * cross-driver sharing. It exists since on a given platform it does uniquely
472 * identify the layout in a simple way for i915-specific userspace, which
481 * This is a tiled layout using 4Kb tiles in row-major layout.
487 * either a square block or a 2:1 unit.
500 * Each CCS tile matches a 1024x512 pixel area of the main surface.
505 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
517 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
518 * main surface. In other words, 4 bits in CCS map to a main surface cache
519 * line pair. The main surface pitch is required to be a multiple of four
528 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
529 * main surface. In other words, 4 bits in CCS map to a main surface cache
530 * line pair. The main surface pitch is required to be a multiple of four
550 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
552 * pitch is required to be a multiple of 4 tile widths.
559 * Macroblocks are laid in a Z-shape, and each pixel data is following the
574 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
575 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
583 * Refers to a compressed variant of the base format that is compressed.
598 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
606 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
618 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
628 * starts at a different base address. Offsets from the base addresses are
648 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
650 * a block depth or height of "4").
671 * hardware support a block width of two gobs, but it is impractical
679 * 19:12 k Page Kind. This value directly maps to a field in the page
692 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
701 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
752 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
754 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
808 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
811 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
814 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
842 * and UV. Some SAND-using hardware stores UV in a separate tiled
881 * necessary to reduce the padding. If a hardware block can't do XOR,
882 * the assumption is that a no-XOR tiling modifier will be created.
889 * AFBC is a proprietary lossless image compression protocol and format.
904 * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
920 * size (in pixels) must be aligned to a multiple of the superblock size.
947 * half of the payload is positioned at a predefined offset from the start
955 * This flag indicates that the payload of each superblock must be stored at a
977 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
989 * can be reduced if a whole superblock is a single color.
996 * Indicates that the buffer is allocated in a layout safe for front-buffer
999 #define AFBC_FORMAT_MOD_DB (1ULL << 10)
1014 * affects the storage mode of the individual superblocks. Note that even a
1023 * AFRC is a proprietary fixed rate image compression protocol and format,
1031 * "coding unit" blocks which are individually compressed to a
1032 * fixed size (in bytes). All coding units within a given plane of a buffer
1047 * to a multiple of the paging tile dimensions.
1063 * Example: 16x4 luma samples in a 'Y' plane
1064 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1067 * Example: 8x8 luma samples in a 'Y' plane
1068 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1071 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
1137 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
1150 * Amlogic uses a proprietary lossless image compression protocol and format
1157 * The underlying storage is considered to be 3 components, 8bit or 10-bit
1184 * - a body content organized in 64x32 superblocks with 4096 bytes per
1186 * - a 32 bytes per 128x64 header block
1207 * The user-space clients should expect a failure while trying to mmap
1285 #define AMD_FMT_MOD_TILE_GFX9_64K_D 10
1324 * and prefers the driver provided color. This necessitates doing a fastclear
1325 * eliminate operation before a process transfers control.