Lines Matching defs:drm_amdgpu_info_device

976 struct drm_amdgpu_info_device {  struct
978 	__u32 device_id;
980 	__u32 chip_rev;
981 	__u32 external_rev;
983 	__u32 pci_rev;
984 	__u32 family;
985 	__u32 num_shader_engines;
986 	__u32 num_shader_arrays_per_engine;
988 	__u32 gpu_counter_freq;
989 	__u64 max_engine_clock;
990 	__u64 max_memory_clock;
992 	__u32 cu_active_number;
994 	__u32 cu_ao_mask;
995 	__u32 cu_bitmap[4][4];
997 	__u32 enabled_rb_pipes_mask;
998 	__u32 num_rb_pipes;
999 	__u32 num_hw_gfx_contexts;
1000 	__u32 _pad;
1001 	__u64 ids_flags;
1003 	__u64 virtual_address_offset;
1005 	__u64 virtual_address_max;
1007 	__u32 virtual_address_alignment;
1009 	__u32 pte_fragment_size;
1010 	__u32 gart_page_size;
1012 	__u32 ce_ram_size;
1014 	__u32 vram_type;
1016 	__u32 vram_bit_width;
1018 	__u32 vce_harvest_config;
1020 	__u32 gc_double_offchip_lds_buf;
1022 	__u64 prim_buf_gpu_addr;
1024 	__u64 pos_buf_gpu_addr;
1026 	__u64 cntl_sb_buf_gpu_addr;
1028 	__u64 param_buf_gpu_addr;
1029 	__u32 prim_buf_size;
1030 	__u32 pos_buf_size;
1031 	__u32 cntl_sb_buf_size;
1032 	__u32 param_buf_size;
1034 	__u32 wave_front_size;
1036 	__u32 num_shader_visible_vgprs;
1038 	__u32 num_cu_per_sh;
1040 	__u32 num_tcc_blocks;
1042 	__u32 gs_vgt_table_depth;
1044 	__u32 gs_prim_buffer_depth;
1046 	__u32 max_gs_waves_per_vgt;
1047 	__u32 _pad1;
1049 	__u32 cu_ao_bitmap[4][4];
1051 	__u64 high_va_offset;
1053 	__u64 high_va_max;
1055 	__u32 pa_sc_tile_steering_override;
1057 	__u64 tcc_disabled_mask;