Lines Matching +full:power +full:- +full:down
1 /* SPDX-License-Identifier: GPL-2.0-only */
32 #define DDR3PHY_ACIOCR_CSPDD_CS0 (1 << 18) /* CS#[0] Power Down Driver */
33 #define DDR3PHY_ACIOCR_CKPDD_CK0 (1 << 8) /* CK[0] Power Down Driver */
34 #define DDR3PHY_ACIORC_ACPDD (1 << 3) /* AC Power Down Driver */
37 #define DDR3PHY_DXCCR_DXPDR (1 << 3) /* Data Power Down Receiver */
40 #define DDR3PHY_DSGCR_ODTPDD_ODT0 (1 << 20) /* ODT[0] Power Down Driver */
46 #define UDDRC_STAT_SELFREF_TYPE_DIS (0x0 << 4) /* SDRAM is not in Self-refresh */
47 #define UDDRC_STAT_SELFREF_TYPE_PHY (0x1 << 4) /* SDRAM is in Self-refresh, which was caused by PH…
48 …_SELFREF_TYPE_SW (0x2 << 4) /* SDRAM is in Self-refresh, which was not caused solely under Automat…
49 …_STAT_SELFREF_TYPE_AUTO (0x3 << 4) /* SDRAM is in Self-refresh, which was caused by Automatic Self…
50 #define UDDRC_STAT_SELFREF_TYPE_MSK (0x3 << 4) /* Self-refresh type mask */
53 #define UDDRC_STAT_OPMODE_PWRDOWN (0x2 << 0) /* Power-down */
54 #define UDDRC_STAT_OPMODE_SELF_REFRESH (0x3 << 0) /* Self-refresh */
57 #define UDDRC_PWRCTL (0x30) /* UDDRC Low Power Control Register */
58 #define UDDRC_PWRCTRL_SELFREF_SW (1 << 5) /* Software self-refresh */
64 #define UDDRC_SWCTRL_SW_DONE (1 << 0) /* Enable quasi-dynamic register programming outside reset …