Lines Matching +full:1 +full:kib
26 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
42 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
43 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
44 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
46 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
72 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
73 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
74 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
104 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
117 #define SR_WEL BIT(1) /* Write enable latch */
120 #define SR_BP1 BIT(3) /* Block protect 1 */
139 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
142 #define FSR_PT_ERR BIT(1) /* Protection error bit */
145 #define SR2_QUAD_EN_BIT1 BIT(1)
146 #define SR2_LB1 BIT(3) /* Security Register Lock Bit 1 */
181 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
182 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
183 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
184 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
185 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
186 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
187 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
192 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
193 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
194 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
195 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
245 #define SNOR_HWCAPS_READ_FAST BIT(1)
271 * legacy SPI 1-1-1 protocol.