33 	u8			sup_pclk;	/* 1 :SH7757, 0: SH7724/SH7372 */
38 #define MMCIF_CE_CMD_SET	0x00000000
39 #define MMCIF_CE_ARG		0x00000008
40 #define MMCIF_CE_ARG_CMD12	0x0000000C
41 #define MMCIF_CE_CMD_CTRL	0x00000010
42 #define MMCIF_CE_BLOCK_SET	0x00000014
43 #define MMCIF_CE_CLK_CTRL	0x00000018
44 #define MMCIF_CE_BUF_ACC	0x0000001C
45 #define MMCIF_CE_RESP3		0x00000020
46 #define MMCIF_CE_RESP2		0x00000024
47 #define MMCIF_CE_RESP1		0x00000028
48 #define MMCIF_CE_RESP0		0x0000002C
49 #define MMCIF_CE_RESP_CMD12	0x00000030
50 #define MMCIF_CE_DATA		0x00000034
51 #define MMCIF_CE_INT		0x00000040
52 #define MMCIF_CE_INT_MASK	0x00000044
53 #define MMCIF_CE_HOST_STS1	0x00000048
54 #define MMCIF_CE_HOST_STS2	0x0000004C
55 #define MMCIF_CE_CLK_CTRL2	0x00000070
56 #define MMCIF_CE_VERSION	0x0000007C
61 #define BUF_ACC_BUSW_32		(0 << 17)
67 #define CLK_CLEAR		(0xf << 16)
68 #define CLK_SUP_PCLK		(0xf << 16)
73 #define SRBSYTO_29		(0xf << 8) /* resp busy timeout */
74 #define SRWDTO_29		(0xf << 4) /* read/write timeout */
75 #define SCCSTO_29		(0xf << 0) /* ccs timeout */
79 #define SOFT_RST_OFF		0
96 	sh_mmcif_writel(base, MMCIF_CE_INT, 0);  in sh_mmcif_boot_cmd_send()
106 	for (cnt = 0; cnt < 1000000; cnt++) {  in sh_mmcif_boot_cmd_poll()
110 			return 0;  in sh_mmcif_boot_cmd_poll()
121 	return sh_mmcif_boot_cmd_poll(base, 0x00010000);  in sh_mmcif_boot_cmd()
131 	sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000);  in sh_mmcif_boot_do_read_single()
133 	if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900)  in sh_mmcif_boot_do_read_single()
137 	sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS);  in sh_mmcif_boot_do_read_single()
138 	if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0)  in sh_mmcif_boot_do_read_single()
141 	for (k = 0; k < (SH_MMCIF_BBS / 4); k++)  in sh_mmcif_boot_do_read_single()
144 	return 0;  in sh_mmcif_boot_do_read_single()
153 	int ret = 0;  in sh_mmcif_boot_do_read()
161 	sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);  in sh_mmcif_boot_do_read()
164 	sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);  in sh_mmcif_boot_do_read()
167 	sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);  in sh_mmcif_boot_do_read()
169 	for (k = 0; !ret && k < nr_blocks; k++)  in sh_mmcif_boot_do_read()
194 	sh_mmcif_boot_cmd(base, 0x00000040, 0);  in sh_mmcif_boot_init()
198 		sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */  in sh_mmcif_boot_init()
199 	} while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000)  in sh_mmcif_boot_init()
200 		 != 0x80000000);  in sh_mmcif_boot_init()
203 	sh_mmcif_boot_cmd(base, 0x02806040, 0);  in sh_mmcif_boot_init()
206 	sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);  in sh_mmcif_boot_init()