1218 #define MLX5_CAP_GEN(mdev, cap) \  argument
1219 	MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1221 #define MLX5_CAP_GEN_64(mdev, cap) \  argument
1222 	MLX5_GET64(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1224 #define MLX5_CAP_GEN_MAX(mdev, cap) \  argument
1225 	MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->max, cap)
1227 #define MLX5_CAP_GEN_2(mdev, cap) \  argument
1228 	MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1230 #define MLX5_CAP_GEN_2_64(mdev, cap) \  argument
1231 	MLX5_GET64(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1233 #define MLX5_CAP_GEN_2_MAX(mdev, cap) \  argument
1234 	MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->max, cap)
1236 #define MLX5_CAP_ETH(mdev, cap) \  argument
1238 		 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->cur, cap)
1240 #define MLX5_CAP_ETH_MAX(mdev, cap) \  argument
1242 		 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->max, cap)
1244 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \  argument
1246 		 mdev->caps.hca[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS]->cur, cap)
1248 #define MLX5_CAP_ROCE(mdev, cap) \  argument
1249 	MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->cur, cap)
1251 #define MLX5_CAP_ROCE_MAX(mdev, cap) \  argument
1252 	MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->max, cap)
1254 #define MLX5_CAP_ATOMIC(mdev, cap) \  argument
1255 	MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->cur, cap)
1257 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \  argument
1258 	MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->max, cap)
1260 #define MLX5_CAP_FLOWTABLE(mdev, cap) \  argument
1261 	MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1263 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \  argument
1264 	MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1266 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \  argument
1267 	MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->max, cap)
1269 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \  argument
1270 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1272 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \  argument
1273 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1275 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \  argument
1276 		MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1278 #define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \  argument
1279 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap)
1281 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \  argument
1282 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1284 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \  argument
1285 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1287 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \  argument
1288 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1290 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \  argument
1291 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1293 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \  argument
1294 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
1296 #define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \  argument
1297 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_rdma.cap)
1299 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \  argument
1300 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap)
1302 #define MLX5_CAP_FLOWTABLE_RDMA_TX_MAX(mdev, cap) \  argument
1303 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_rdma.cap)
1305 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \  argument
1307 		 mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1309 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \  argument
1311 		 mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->max, cap)
1313 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \  argument
1314 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1316 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \  argument
1317 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1319 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \  argument
1320 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1322 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \  argument
1323 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1325 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \  argument
1326 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1328 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \  argument
1329 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1331 #define MLX5_CAP_ESW(mdev, cap) \  argument
1333 		 mdev->caps.hca[MLX5_CAP_ESWITCH]->cur, cap)
1335 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \  argument
1337 		(mdev)->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1339 #define MLX5_CAP_ESW_MAX(mdev, cap) \  argument
1341 		 mdev->caps.hca[MLX5_CAP_ESWITCH]->max, cap)
1343 #define MLX5_CAP_ODP(mdev, cap)\  argument
1344 	MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap)
1346 #define MLX5_CAP_ODP_MAX(mdev, cap)\  argument
1347 	MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->max, cap)
1349 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \  argument
1351 		 mdev->caps.hca[MLX5_CAP_VECTOR_CALC]->cur, cap)
1353 #define MLX5_CAP_QOS(mdev, cap)\  argument
1354 	MLX5_GET(qos_cap, mdev->caps.hca[MLX5_CAP_QOS]->cur, cap)
1356 #define MLX5_CAP_DEBUG(mdev, cap)\  argument
1357 	MLX5_GET(debug_cap, mdev->caps.hca[MLX5_CAP_DEBUG]->cur, cap)
1386 #define MLX5_CAP_FPGA(mdev, cap) \  argument
1387 	MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1389 #define MLX5_CAP64_FPGA(mdev, cap) \  argument
1390 	MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1392 #define MLX5_CAP_DEV_MEM(mdev, cap)\  argument
1393 	MLX5_GET(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1395 #define MLX5_CAP64_DEV_MEM(mdev, cap)\  argument
1396 	MLX5_GET64(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1398 #define MLX5_CAP_TLS(mdev, cap) \  argument
1399 	MLX5_GET(tls_cap, (mdev)->caps.hca[MLX5_CAP_TLS]->cur, cap)
1401 #define MLX5_CAP_DEV_EVENT(mdev, cap)\  argument
1402 	MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca[MLX5_CAP_DEV_EVENT]->cur, cap)
1404 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\  argument
1406 		(mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1408 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\  argument
1410 		(mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1412 #define MLX5_CAP_IPSEC(mdev, cap)\  argument
1413 	MLX5_GET(ipsec_cap, (mdev)->caps.hca[MLX5_CAP_IPSEC]->cur, cap)