1218 #define MLX5_CAP_GEN(mdev, cap) \  argument
1221 #define MLX5_CAP_GEN_64(mdev, cap) \  argument
1224 #define MLX5_CAP_GEN_MAX(mdev, cap) \  argument
1227 #define MLX5_CAP_GEN_2(mdev, cap) \  argument
1230 #define MLX5_CAP_GEN_2_64(mdev, cap) \  argument
1233 #define MLX5_CAP_GEN_2_MAX(mdev, cap) \  argument
1236 #define MLX5_CAP_ETH(mdev, cap) \  argument
1240 #define MLX5_CAP_ETH_MAX(mdev, cap) \  argument
1244 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \  argument
1248 #define MLX5_CAP_ROCE(mdev, cap) \  argument
1251 #define MLX5_CAP_ROCE_MAX(mdev, cap) \  argument
1254 #define MLX5_CAP_ATOMIC(mdev, cap) \  argument
1257 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \  argument
1260 #define MLX5_CAP_FLOWTABLE(mdev, cap) \  argument
1263 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \  argument
1266 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \  argument
1269 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \  argument
1272 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \  argument
1275 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \  argument
1278 #define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \  argument
1281 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \  argument
1284 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \  argument
1287 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \  argument
1290 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \  argument
1293 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \  argument
1296 #define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \  argument
1299 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \  argument
1302 #define MLX5_CAP_FLOWTABLE_RDMA_TX_MAX(mdev, cap) \  argument
1305 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \  argument
1309 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \  argument
1313 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \  argument
1316 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \  argument
1319 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \  argument
1322 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \  argument
1325 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \  argument
1328 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \  argument
1331 #define MLX5_CAP_ESW(mdev, cap) \  argument
1335 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \  argument
1339 #define MLX5_CAP_ESW_MAX(mdev, cap) \  argument
1343 #define MLX5_CAP_ODP(mdev, cap)\  argument
1346 #define MLX5_CAP_ODP_MAX(mdev, cap)\  argument
1349 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \  argument
1353 #define MLX5_CAP_QOS(mdev, cap)\  argument
1356 #define MLX5_CAP_DEBUG(mdev, cap)\  argument
1359 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \  argument
1362 #define MLX5_CAP_PCAM_REG(mdev, reg) \  argument
1365 #define MLX5_CAP_MCAM_REG(mdev, reg) \  argument
1369 #define MLX5_CAP_MCAM_REG1(mdev, reg) \  argument
1373 #define MLX5_CAP_MCAM_REG2(mdev, reg) \  argument
1377 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \  argument
1380 #define MLX5_CAP_QCAM_REG(mdev, fld) \  argument
1383 #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \  argument
1386 #define MLX5_CAP_FPGA(mdev, cap) \  argument
1389 #define MLX5_CAP64_FPGA(mdev, cap) \  argument
1392 #define MLX5_CAP_DEV_MEM(mdev, cap)\  argument
1395 #define MLX5_CAP64_DEV_MEM(mdev, cap)\  argument
1398 #define MLX5_CAP_TLS(mdev, cap) \  argument
1401 #define MLX5_CAP_DEV_EVENT(mdev, cap)\  argument
1404 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\  argument
1408 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\  argument
1412 #define MLX5_CAP_IPSEC(mdev, cap)\  argument