Lines Matching full:ll
154 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
155 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
156 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
157 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
158 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
159 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
160 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
161 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
162 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
163 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
164 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
165 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
166 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
167 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
168 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
169 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
170 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
171 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
172 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
173 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
174 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
175 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
176 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
177 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
178 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
179 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52,
180 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
181 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
182 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
183 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
184 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
188 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
189 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
190 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
191 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
192 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
193 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
194 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
195 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
196 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
197 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
198 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
199 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11,
200 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12,
201 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13,
202 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14,
203 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15,
204 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16,
205 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17,
206 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
207 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19,
208 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
209 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21,
210 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22,
211 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23,
212 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24,
213 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25,
214 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26,
215 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27,
216 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28,
217 MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29,
218 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30,
232 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0,
233 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1
254 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
255 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1,
256 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2,
257 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3