Lines Matching +full:4 +full:x2

29 #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_SSI_SRCK	(0x2 << 30)
34 #define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_DO_SCKR	(0x2 << 28)
38 #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_SSI_STCK	(0x2 << 26)
48 #define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_SSI_STCK	(0x2 << 22)
53 #define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_SSI_SRCK	(0x2 << 20)
58 #define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_STCK	(0x2 << 18)
63 #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_SRCK	(0x2 << 16)
68 #define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK3	(0x2 << 14)
78 #define IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK		BIT(4)
80 #define IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1		BIT(4)
127 #define IMX6Q_GPR1_ADDRS3_128MB			(0x2 << 10)
131 #define IMX6Q_GPR1_ADDRS1_MASK			(0x3 << 4)
139 #define IMX6Q_GPR2_COUNTER_RESET_VAL_4		(0x2 << 20)
144 #define IMX6Q_GPR2_LVDS_CLK_SHIFT_2		(0x2 << 16)
171 #define IMX6Q_GPR2_SPLIT_MODE_EN		BIT(4)
184 #define IMX6Q_GPR3_GPU_DBG_OPENVG		(0x2 << 29)
201 #define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI0	(0x2 << 8)
206 #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0	(0x2 << 6)
208 #define IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT		4
209 #define IMX6Q_GPR3_MIPI_MUX_CTL_MASK		(0x3 << 4)
210 #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0	(0x0 << 4)
211 #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1	(0x1 << 4)
212 #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI0	(0x2 << 4)
213 #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI1	(0x3 << 4)
218 #define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI0	(0x2 << 2)
247 #define IMX6Q_GPR6_IPU1_ID01_WR_QOS_MASK	(0xf << 4)
256 #define IMX6Q_GPR7_IPU2_ID01_WR_QOS_MASK	(0xf << 4)
286 #define IMX6Q_GPR10_OCRAM_TZ_EN_MASK		BIT(4)
290 #define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0	(0x2 << 2)
295 #define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0	(0x2 << 0)
304 #define IMX6Q_GPR12_LOS_LEVEL			(0x1f << 4)
313 #define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB	(0x2 << 24)
329 #define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_4F	(0x2 << 16)
338 #define IMX6Q_GPR13_SATA_TX_ATTEN_12_16		(0x2 << 11)
345 #define IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB	(0x2 << 7)
420 #define IMX6SX_GPR4_FEC_ENET2_STOP_REQ			(0x1 << 4)
429 #define IMX6SX_GPR5_CSI2_MUX_CTRL_VDAC_TO_CSI		(0x2 << 27)
435 #define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK			(0x3 << 4)
436 #define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN		(0x0 << 4)
437 #define IMX6SX_GPR5_CSI1_MUX_CTRL_CVD			(0x1 << 4)
438 #define IMX6SX_GPR5_CSI1_MUX_CTRL_VDAC_TO_CSI		(0x2 << 4)
439 #define IMX6SX_GPR5_CSI1_MUX_CTRL_GND			(0x3 << 4)
451 #define IMX6SX_GPR12_PCIE_RX_EQ_2			(0x2 << 0)