Lines Matching +full:0 +full:x7f
10 #define MT6359_SWCID 0xa
11 #define MT6359_MISC_TOP_INT_CON0 0x188
12 #define MT6359_MISC_TOP_INT_STATUS0 0x194
13 #define MT6359_TOP_INT_STATUS0 0x19e
14 #define MT6359_SCK_TOP_INT_CON0 0x528
15 #define MT6359_SCK_TOP_INT_STATUS0 0x534
16 #define MT6359_EOSC_CALI_CON0 0x53a
17 #define MT6359_EOSC_CALI_CON1 0x53c
18 #define MT6359_RTC_MIX_CON0 0x53e
19 #define MT6359_RTC_MIX_CON1 0x540
20 #define MT6359_RTC_MIX_CON2 0x542
21 #define MT6359_RTC_DSN_ID 0x580
22 #define MT6359_RTC_DSN_REV0 0x582
23 #define MT6359_RTC_DBI 0x584
24 #define MT6359_RTC_DXI 0x586
25 #define MT6359_RTC_BBPU 0x588
26 #define MT6359_RTC_IRQ_STA 0x58a
27 #define MT6359_RTC_IRQ_EN 0x58c
28 #define MT6359_RTC_CII_EN 0x58e
29 #define MT6359_RTC_AL_MASK 0x590
30 #define MT6359_RTC_TC_SEC 0x592
31 #define MT6359_RTC_TC_MIN 0x594
32 #define MT6359_RTC_TC_HOU 0x596
33 #define MT6359_RTC_TC_DOM 0x598
34 #define MT6359_RTC_TC_DOW 0x59a
35 #define MT6359_RTC_TC_MTH 0x59c
36 #define MT6359_RTC_TC_YEA 0x59e
37 #define MT6359_RTC_AL_SEC 0x5a0
38 #define MT6359_RTC_AL_MIN 0x5a2
39 #define MT6359_RTC_AL_HOU 0x5a4
40 #define MT6359_RTC_AL_DOM 0x5a6
41 #define MT6359_RTC_AL_DOW 0x5a8
42 #define MT6359_RTC_AL_MTH 0x5aa
43 #define MT6359_RTC_AL_YEA 0x5ac
44 #define MT6359_RTC_OSC32CON 0x5ae
45 #define MT6359_RTC_POWERKEY1 0x5b0
46 #define MT6359_RTC_POWERKEY2 0x5b2
47 #define MT6359_RTC_PDN1 0x5b4
48 #define MT6359_RTC_PDN2 0x5b6
49 #define MT6359_RTC_SPAR0 0x5b8
50 #define MT6359_RTC_SPAR1 0x5ba
51 #define MT6359_RTC_PROT 0x5bc
52 #define MT6359_RTC_DIFF 0x5be
53 #define MT6359_RTC_CALI 0x5c0
54 #define MT6359_RTC_WRTGR 0x5c2
55 #define MT6359_RTC_CON 0x5c4
56 #define MT6359_RTC_SEC_CTRL 0x5c6
57 #define MT6359_RTC_INT_CNT 0x5c8
58 #define MT6359_RTC_SEC_DAT0 0x5ca
59 #define MT6359_RTC_SEC_DAT1 0x5cc
60 #define MT6359_RTC_SEC_DAT2 0x5ce
61 #define MT6359_RTC_SEC_DSN_ID 0x600
62 #define MT6359_RTC_SEC_DSN_REV0 0x602
63 #define MT6359_RTC_SEC_DBI 0x604
64 #define MT6359_RTC_SEC_DXI 0x606
65 #define MT6359_RTC_TC_SEC_SEC 0x608
66 #define MT6359_RTC_TC_MIN_SEC 0x60a
67 #define MT6359_RTC_TC_HOU_SEC 0x60c
68 #define MT6359_RTC_TC_DOM_SEC 0x60e
69 #define MT6359_RTC_TC_DOW_SEC 0x610
70 #define MT6359_RTC_TC_MTH_SEC 0x612
71 #define MT6359_RTC_TC_YEA_SEC 0x614
72 #define MT6359_RTC_SEC_CK_PDN 0x616
73 #define MT6359_RTC_SEC_WRTGR 0x618
74 #define MT6359_PSC_TOP_INT_CON0 0x910
75 #define MT6359_PSC_TOP_INT_STATUS0 0x91c
76 #define MT6359_BM_TOP_INT_CON0 0xc32
77 #define MT6359_BM_TOP_INT_CON1 0xc38
78 #define MT6359_BM_TOP_INT_STATUS0 0xc4a
79 #define MT6359_BM_TOP_INT_STATUS1 0xc4c
80 #define MT6359_HK_TOP_INT_CON0 0xf92
81 #define MT6359_HK_TOP_INT_STATUS0 0xf9e
82 #define MT6359_BUCK_TOP_INT_CON0 0x1418
83 #define MT6359_BUCK_TOP_INT_STATUS0 0x1424
84 #define MT6359_BUCK_VPU_CON0 0x1488
85 #define MT6359_BUCK_VPU_DBG0 0x14a6
86 #define MT6359_BUCK_VPU_DBG1 0x14a8
87 #define MT6359_BUCK_VPU_ELR0 0x14ac
88 #define MT6359_BUCK_VCORE_CON0 0x1508
89 #define MT6359_BUCK_VCORE_DBG0 0x1526
90 #define MT6359_BUCK_VCORE_DBG1 0x1528
91 #define MT6359_BUCK_VCORE_SSHUB_CON0 0x152a
92 #define MT6359_BUCK_VCORE_ELR0 0x1534
93 #define MT6359_BUCK_VGPU11_CON0 0x1588
94 #define MT6359_BUCK_VGPU11_DBG0 0x15a6
95 #define MT6359_BUCK_VGPU11_DBG1 0x15a8
96 #define MT6359_BUCK_VGPU11_ELR0 0x15ac
97 #define MT6359_BUCK_VMODEM_CON0 0x1688
98 #define MT6359_BUCK_VMODEM_DBG0 0x16a6
99 #define MT6359_BUCK_VMODEM_DBG1 0x16a8
100 #define MT6359_BUCK_VMODEM_ELR0 0x16ae
101 #define MT6359_BUCK_VPROC1_CON0 0x1708
102 #define MT6359_BUCK_VPROC1_DBG0 0x1726
103 #define MT6359_BUCK_VPROC1_DBG1 0x1728
104 #define MT6359_BUCK_VPROC1_ELR0 0x172e
105 #define MT6359_BUCK_VPROC2_CON0 0x1788
106 #define MT6359_BUCK_VPROC2_DBG0 0x17a6
107 #define MT6359_BUCK_VPROC2_DBG1 0x17a8
108 #define MT6359_BUCK_VPROC2_ELR0 0x17b2
109 #define MT6359_BUCK_VS1_CON0 0x1808
110 #define MT6359_BUCK_VS1_DBG0 0x1826
111 #define MT6359_BUCK_VS1_DBG1 0x1828
112 #define MT6359_BUCK_VS1_ELR0 0x1834
113 #define MT6359_BUCK_VS2_CON0 0x1888
114 #define MT6359_BUCK_VS2_DBG0 0x18a6
115 #define MT6359_BUCK_VS2_DBG1 0x18a8
116 #define MT6359_BUCK_VS2_ELR0 0x18b4
117 #define MT6359_BUCK_VPA_CON0 0x1908
118 #define MT6359_BUCK_VPA_CON1 0x190e
119 #define MT6359_BUCK_VPA_CFG0 0x1910
120 #define MT6359_BUCK_VPA_CFG1 0x1912
121 #define MT6359_BUCK_VPA_DBG0 0x1914
122 #define MT6359_BUCK_VPA_DBG1 0x1916
123 #define MT6359_VGPUVCORE_ANA_CON2 0x198e
124 #define MT6359_VGPUVCORE_ANA_CON13 0x19a4
125 #define MT6359_VPROC1_ANA_CON3 0x19b2
126 #define MT6359_VPROC2_ANA_CON3 0x1a0e
127 #define MT6359_VMODEM_ANA_CON3 0x1a1a
128 #define MT6359_VPU_ANA_CON3 0x1a26
129 #define MT6359_VS1_ANA_CON0 0x1a2c
130 #define MT6359_VS2_ANA_CON0 0x1a34
131 #define MT6359_VPA_ANA_CON0 0x1a3c
132 #define MT6359_LDO_TOP_INT_CON0 0x1b14
133 #define MT6359_LDO_TOP_INT_CON1 0x1b1a
134 #define MT6359_LDO_TOP_INT_STATUS0 0x1b28
135 #define MT6359_LDO_TOP_INT_STATUS1 0x1b2a
136 #define MT6359_LDO_VSRAM_PROC1_ELR 0x1b40
137 #define MT6359_LDO_VSRAM_PROC2_ELR 0x1b42
138 #define MT6359_LDO_VSRAM_OTHERS_ELR 0x1b44
139 #define MT6359_LDO_VSRAM_MD_ELR 0x1b46
140 #define MT6359_LDO_VFE28_CON0 0x1b88
141 #define MT6359_LDO_VFE28_MON 0x1b8a
142 #define MT6359_LDO_VXO22_CON0 0x1b98
143 #define MT6359_LDO_VXO22_MON 0x1b9a
144 #define MT6359_LDO_VRF18_CON0 0x1ba8
145 #define MT6359_LDO_VRF18_MON 0x1baa
146 #define MT6359_LDO_VRF12_CON0 0x1bb8
147 #define MT6359_LDO_VRF12_MON 0x1bba
148 #define MT6359_LDO_VEFUSE_CON0 0x1bc8
149 #define MT6359_LDO_VEFUSE_MON 0x1bca
150 #define MT6359_LDO_VCN33_1_CON0 0x1bd8
151 #define MT6359_LDO_VCN33_1_MON 0x1bda
152 #define MT6359_LDO_VCN33_1_MULTI_SW 0x1be8
153 #define MT6359_LDO_VCN33_2_CON0 0x1c08
154 #define MT6359_LDO_VCN33_2_MON 0x1c0a
155 #define MT6359_LDO_VCN33_2_MULTI_SW 0x1c18
156 #define MT6359_LDO_VCN13_CON0 0x1c1a
157 #define MT6359_LDO_VCN13_MON 0x1c1c
158 #define MT6359_LDO_VCN18_CON0 0x1c2a
159 #define MT6359_LDO_VCN18_MON 0x1c2c
160 #define MT6359_LDO_VA09_CON0 0x1c3a
161 #define MT6359_LDO_VA09_MON 0x1c3c
162 #define MT6359_LDO_VCAMIO_CON0 0x1c4a
163 #define MT6359_LDO_VCAMIO_MON 0x1c4c
164 #define MT6359_LDO_VA12_CON0 0x1c5a
165 #define MT6359_LDO_VA12_MON 0x1c5c
166 #define MT6359_LDO_VAUX18_CON0 0x1c88
167 #define MT6359_LDO_VAUX18_MON 0x1c8a
168 #define MT6359_LDO_VAUD18_CON0 0x1c98
169 #define MT6359_LDO_VAUD18_MON 0x1c9a
170 #define MT6359_LDO_VIO18_CON0 0x1ca8
171 #define MT6359_LDO_VIO18_MON 0x1caa
172 #define MT6359_LDO_VEMC_CON0 0x1cb8
173 #define MT6359_LDO_VEMC_MON 0x1cba
174 #define MT6359_LDO_VSIM1_CON0 0x1cc8
175 #define MT6359_LDO_VSIM1_MON 0x1cca
176 #define MT6359_LDO_VSIM2_CON0 0x1cd8
177 #define MT6359_LDO_VSIM2_MON 0x1cda
178 #define MT6359_LDO_VUSB_CON0 0x1d08
179 #define MT6359_LDO_VUSB_MON 0x1d0a
180 #define MT6359_LDO_VUSB_MULTI_SW 0x1d18
181 #define MT6359_LDO_VRFCK_CON0 0x1d1a
182 #define MT6359_LDO_VRFCK_MON 0x1d1c
183 #define MT6359_LDO_VBBCK_CON0 0x1d2a
184 #define MT6359_LDO_VBBCK_MON 0x1d2c
185 #define MT6359_LDO_VBIF28_CON0 0x1d3a
186 #define MT6359_LDO_VBIF28_MON 0x1d3c
187 #define MT6359_LDO_VIBR_CON0 0x1d4a
188 #define MT6359_LDO_VIBR_MON 0x1d4c
189 #define MT6359_LDO_VIO28_CON0 0x1d5a
190 #define MT6359_LDO_VIO28_MON 0x1d5c
191 #define MT6359_LDO_VM18_CON0 0x1d88
192 #define MT6359_LDO_VM18_MON 0x1d8a
193 #define MT6359_LDO_VUFS_CON0 0x1d98
194 #define MT6359_LDO_VUFS_MON 0x1d9a
195 #define MT6359_LDO_VSRAM_PROC1_CON0 0x1e88
196 #define MT6359_LDO_VSRAM_PROC1_MON 0x1e8a
197 #define MT6359_LDO_VSRAM_PROC1_VOSEL1 0x1e8e
198 #define MT6359_LDO_VSRAM_PROC2_CON0 0x1ea6
199 #define MT6359_LDO_VSRAM_PROC2_MON 0x1ea8
200 #define MT6359_LDO_VSRAM_PROC2_VOSEL1 0x1eac
201 #define MT6359_LDO_VSRAM_OTHERS_CON0 0x1f08
202 #define MT6359_LDO_VSRAM_OTHERS_MON 0x1f0a
203 #define MT6359_LDO_VSRAM_OTHERS_VOSEL1 0x1f0e
204 #define MT6359_LDO_VSRAM_OTHERS_SSHUB 0x1f26
205 #define MT6359_LDO_VSRAM_MD_CON0 0x1f2c
206 #define MT6359_LDO_VSRAM_MD_MON 0x1f2e
207 #define MT6359_LDO_VSRAM_MD_VOSEL1 0x1f32
208 #define MT6359_VFE28_ANA_CON0 0x1f88
209 #define MT6359_VAUX18_ANA_CON0 0x1f8c
210 #define MT6359_VUSB_ANA_CON0 0x1f90
211 #define MT6359_VBIF28_ANA_CON0 0x1f94
212 #define MT6359_VCN33_1_ANA_CON0 0x1f98
213 #define MT6359_VCN33_2_ANA_CON0 0x1f9c
214 #define MT6359_VEMC_ANA_CON0 0x1fa0
215 #define MT6359_VSIM1_ANA_CON0 0x1fa4
216 #define MT6359_VSIM2_ANA_CON0 0x1fa8
217 #define MT6359_VIO28_ANA_CON0 0x1fac
218 #define MT6359_VIBR_ANA_CON0 0x1fb0
219 #define MT6359_VRF18_ANA_CON0 0x2008
220 #define MT6359_VEFUSE_ANA_CON0 0x200c
221 #define MT6359_VCN18_ANA_CON0 0x2010
222 #define MT6359_VCAMIO_ANA_CON0 0x2014
223 #define MT6359_VAUD18_ANA_CON0 0x2018
224 #define MT6359_VIO18_ANA_CON0 0x201c
225 #define MT6359_VM18_ANA_CON0 0x2020
226 #define MT6359_VUFS_ANA_CON0 0x2024
227 #define MT6359_VRF12_ANA_CON0 0x202a
228 #define MT6359_VCN13_ANA_CON0 0x202e
229 #define MT6359_VA09_ANA_CON0 0x2032
230 #define MT6359_VA12_ANA_CON0 0x2036
231 #define MT6359_VXO22_ANA_CON0 0x2088
232 #define MT6359_VRFCK_ANA_CON0 0x208c
233 #define MT6359_VBBCK_ANA_CON0 0x2094
234 #define MT6359_AUD_TOP_INT_CON0 0x2328
235 #define MT6359_AUD_TOP_INT_STATUS0 0x2334
241 #define MT6359_DA_VPU_VOSEL_MASK 0x7F
242 #define MT6359_DA_VPU_VOSEL_SHIFT 0
245 #define MT6359_RG_BUCK_VPU_VOSEL_MASK 0x7F
246 #define MT6359_RG_BUCK_VPU_VOSEL_SHIFT 0
251 #define MT6359_DA_VCORE_VOSEL_MASK 0x7F
252 #define MT6359_DA_VCORE_VOSEL_SHIFT 0
256 #define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_MASK 0x7F
259 #define MT6359_RG_BUCK_VCORE_VOSEL_MASK 0x7F
260 #define MT6359_RG_BUCK_VCORE_VOSEL_SHIFT 0
265 #define MT6359_DA_VGPU11_VOSEL_MASK 0x7F
266 #define MT6359_DA_VGPU11_VOSEL_SHIFT 0
269 #define MT6359_RG_BUCK_VGPU11_VOSEL_MASK 0x7F
270 #define MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT 0
275 #define MT6359_DA_VMODEM_VOSEL_MASK 0x7F
276 #define MT6359_DA_VMODEM_VOSEL_SHIFT 0
279 #define MT6359_RG_BUCK_VMODEM_VOSEL_MASK 0x7F
280 #define MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT 0
285 #define MT6359_DA_VPROC1_VOSEL_MASK 0x7F
286 #define MT6359_DA_VPROC1_VOSEL_SHIFT 0
289 #define MT6359_RG_BUCK_VPROC1_VOSEL_MASK 0x7F
290 #define MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT 0
295 #define MT6359_DA_VPROC2_VOSEL_MASK 0x7F
296 #define MT6359_DA_VPROC2_VOSEL_SHIFT 0
299 #define MT6359_RG_BUCK_VPROC2_VOSEL_MASK 0x7F
300 #define MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT 0
305 #define MT6359_DA_VS1_VOSEL_MASK 0x7F
306 #define MT6359_DA_VS1_VOSEL_SHIFT 0
309 #define MT6359_RG_BUCK_VS1_VOSEL_MASK 0x7F
310 #define MT6359_RG_BUCK_VS1_VOSEL_SHIFT 0
315 #define MT6359_DA_VS2_VOSEL_MASK 0x7F
316 #define MT6359_DA_VS2_VOSEL_SHIFT 0
319 #define MT6359_RG_BUCK_VS2_VOSEL_MASK 0x7F
320 #define MT6359_RG_BUCK_VS2_VOSEL_SHIFT 0
325 #define MT6359_RG_BUCK_VPA_VOSEL_MASK 0x3F
326 #define MT6359_RG_BUCK_VPA_VOSEL_SHIFT 0
328 #define MT6359_DA_VPA_VOSEL_MASK 0x3F
329 #define MT6359_DA_VPA_VOSEL_SHIFT 0
350 #define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK 0x7F
351 #define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT 0
353 #define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK 0x7F
354 #define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT 0
356 #define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK 0x7F
357 #define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT 0
359 #define MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK 0x7F
360 #define MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT 0
364 #define MT6359_RG_LDO_VXO22_EN_SHIFT 0
367 #define MT6359_RG_LDO_VRF18_EN_SHIFT 0
370 #define MT6359_RG_LDO_VRF12_EN_SHIFT 0
373 #define MT6359_RG_LDO_VEFUSE_EN_SHIFT 0
376 #define MT6359_RG_LDO_VCN33_1_EN_0_MASK 0x1
377 #define MT6359_RG_LDO_VCN33_1_EN_0_SHIFT 0
382 #define MT6359_RG_LDO_VCN33_2_EN_0_SHIFT 0
385 #define MT6359_RG_LDO_VCN33_2_EN_1_MASK 0x1
388 #define MT6359_RG_LDO_VCN13_EN_SHIFT 0
393 #define MT6359_RG_LDO_VA09_EN_SHIFT 0
396 #define MT6359_RG_LDO_VCAMIO_EN_SHIFT 0
399 #define MT6359_RG_LDO_VA12_EN_SHIFT 0
406 #define MT6359_RG_LDO_VIO18_EN_SHIFT 0
409 #define MT6359_RG_LDO_VEMC_EN_SHIFT 0
412 #define MT6359_RG_LDO_VSIM1_EN_SHIFT 0
415 #define MT6359_RG_LDO_VSIM2_EN_SHIFT 0
418 #define MT6359_RG_LDO_VUSB_EN_0_MASK 0x1
419 #define MT6359_RG_LDO_VUSB_EN_0_SHIFT 0
422 #define MT6359_RG_LDO_VUSB_EN_1_MASK 0x1
425 #define MT6359_RG_LDO_VRFCK_EN_SHIFT 0
428 #define MT6359_RG_LDO_VBBCK_EN_SHIFT 0
433 #define MT6359_RG_LDO_VIBR_EN_SHIFT 0
436 #define MT6359_RG_LDO_VIO28_EN_SHIFT 0
439 #define MT6359_RG_LDO_VM18_EN_SHIFT 0
442 #define MT6359_RG_LDO_VUFS_EN_SHIFT 0
447 #define MT6359_DA_VSRAM_PROC1_VOSEL_MASK 0x7F
452 #define MT6359_DA_VSRAM_PROC2_VOSEL_MASK 0x7F
457 #define MT6359_DA_VSRAM_OTHERS_VOSEL_MASK 0x7F
461 #define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK 0x7F
466 #define MT6359_DA_VSRAM_MD_VOSEL_MASK 0x7F
469 #define MT6359_RG_VCN33_1_VOSEL_MASK 0xF
472 #define MT6359_RG_VCN33_2_VOSEL_MASK 0xF
475 #define MT6359_RG_VEMC_VOSEL_MASK 0xF
478 #define MT6359_RG_VSIM1_VOSEL_MASK 0xF
481 #define MT6359_RG_VSIM2_VOSEL_MASK 0xF
484 #define MT6359_RG_VIO28_VOSEL_MASK 0xF
487 #define MT6359_RG_VIBR_VOSEL_MASK 0xF
490 #define MT6359_RG_VRF18_VOSEL_MASK 0xF
493 #define MT6359_RG_VEFUSE_VOSEL_MASK 0xF
496 #define MT6359_RG_VCAMIO_VOSEL_MASK 0xF
499 #define MT6359_RG_VIO18_VOSEL_MASK 0xF
502 #define MT6359_RG_VM18_VOSEL_MASK 0xF
505 #define MT6359_RG_VUFS_VOSEL_MASK 0xF
508 #define MT6359_RG_VRF12_VOSEL_MASK 0xF
511 #define MT6359_RG_VCN13_VOSEL_MASK 0xF
514 #define MT6359_RG_VA09_VOSEL_MASK 0xF
517 #define MT6359_RG_VA12_VOSEL_MASK 0xF
520 #define MT6359_RG_VXO22_VOSEL_MASK 0xF
523 #define MT6359_RG_VRFCK_VOSEL_MASK 0xF
526 #define MT6359_RG_VBBCK_VOSEL_MASK 0xF