Lines Matching full:definitions

452 /* Bit definitions for the MAJ_REL register */
457 /* Bit definitions for the USER_GPIO0_TO_7_STATUS register */
467 /* Bit definitions for the USER_GPIO8_TO_15_STATUS register */
477 /* Bit definitions for the GPIO0_TO_7_OUT register */
487 /* Bit definitions for the GPIO8_TO_15_OUT register */
497 /* Bit definitions for the DPLL_TOD_SYNC_CFG register */
502 /* Bit definitions for the DPLL_MODE register */
509 /* Bit definitions for the GPIO_CFG_GBL register */
513 /* Bit definitions for the GPIO_DCO_INC_DEC register */
517 /* Bit definitions for the GPIO_OUT_CTRL_0 register */
527 /* Bit definitions for the GPIO_OUT_CTRL_1 register */
537 /* Bit definitions for the GPIO_TOD_TRIG register */
543 /* Bit definitions for the GPIO_DPLL_INDICATOR register */
547 /* Bit definitions for the GPIO_LOS_INDICATOR register */
553 /* Bit definitions for the GPIO_REF_INPUT_DSQ_0 register */
563 /* Bit definitions for the GPIO_REF_INPUT_DSQ_1 register */
573 /* Bit definitions for the GPIO_REF_INPUT_DSQ_2 register */
583 /* Bit definitions for the GPIO_REF_INPUT_DSQ_3 register */
587 /* Bit definitions for the GPIO_TOD_NOTIFICATION_CFG register */
593 /* Bit definitions for the GPIO_CTRL register */
601 /* Bit definitions for the OUT_CTRL_1 register */
610 /* Bit definitions for the TOD_CFG register */
615 /* Bit definitions for the TOD_WRITE_SELECT_CFG_0 register */
621 /* Bit definitions for the TOD_WRITE_CMD register */
628 /* Bit definitions for the TOD_READ_PRIMARY_SEL_CFG_0 register */
634 /* Bit definitions for the TOD_READ_PRIMARY_CMD register */
639 /* Bit definitions for the DPLL_CTRL_COMBO_MASTER_CFG register */
642 /* Bit definitions for DPLL_SYS_STATUS register */
645 /* Bit definitions for SYS_APLL_STATUS register */
650 /* Bit definitions for the DPLL0_STATUS register */