Lines Matching +full:0 +full:x103

11 #define DPLL1_TOD_CNFG 0x134
12 #define DPLL2_TOD_CNFG 0x1B4
14 #define DPLL1_TOD_STS 0x10B
15 #define DPLL2_TOD_STS 0x18B
17 #define DPLL1_TOD_TRIGGER 0x115
18 #define DPLL2_TOD_TRIGGER 0x195
20 #define DPLL1_OPERATING_MODE_CNFG 0x120
21 #define DPLL2_OPERATING_MODE_CNFG 0x1A0
23 #define DPLL1_HOLDOVER_FREQ_CNFG 0x12C
24 #define DPLL2_HOLDOVER_FREQ_CNFG 0x1AC
26 #define DPLL1_PHASE_OFFSET_CNFG 0x143
27 #define DPLL2_PHASE_OFFSET_CNFG 0x1C3
29 #define DPLL1_SYNC_EDGE_CNFG 0x140
30 #define DPLL2_SYNC_EDGE_CNFG 0x1C0
32 #define DPLL1_INPUT_MODE_CNFG 0x116
33 #define DPLL2_INPUT_MODE_CNFG 0x196
35 #define DPLL1_OPERATING_STS 0x102
36 #define DPLL2_OPERATING_STS 0x182
38 #define DPLL1_CURRENT_FREQ_STS 0x103
39 #define DPLL2_CURRENT_FREQ_STS 0x183
41 #define REG_SOFT_RESET 0X381
43 #define OUT_MUX_CNFG(outn) REG_ADDR(0x6, (0xC * (outn)))
51 #define PLL_MODE_SHIFT		(0)
52 #define PLL_MODE_MASK		(0x1F)
55 #define COMBO_MODE_MASK		(0x3)
58 #define OPERATING_STS_MASK	(0x7)
59 #define OPERATING_STS_SHIFT	(0x0)
62 #define READ_TRIGGER_MASK	(0xF)
63 #define READ_TRIGGER_SHIFT	(0x0)
64 #define WRITE_TRIGGER_MASK	(0xF0)
65 #define WRITE_TRIGGER_SHIFT	(0x4)
71 	PLL_MODE_MIN = 0,
85 	HW_TOD_TRIG_SEL_MIN = 0,