Lines Matching defs:intel_iommu

578 struct intel_iommu {  struct
579 	void __iomem	*reg; /* Pointer to hardware regs, virtual addr */
580 	u64 		reg_phys; /* physical address of hw register set */
581 	u64		reg_size; /* size of hw register set */
582 	u64		cap;
583 	u64		ecap;
584 	u64		vccap;
585 	u32		gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
586 	raw_spinlock_t	register_lock; /* protect register handling */
587 	int		seq_id;	/* sequence id of the iommu */
588 	int		agaw; /* agaw of this iommu */
589 	int		msagaw; /* max sagaw of this iommu */
590 	unsigned int 	irq, pr_irq;
591 	u16		segment;     /* PCI segment# */
592 	unsigned char 	name[13];    /* Device Name */
595 	unsigned long 	*domain_ids; /* bitmap of domains */
596 	struct dmar_domain ***domains; /* ptr to domains */
597 	spinlock_t	lock; /* protect context, domain ids */
598 	struct root_entry *root_entry; /* virtual address */
600 	struct iommu_flush flush;
603 	struct page_req_dsc *prq;
604 	unsigned char prq_name[16];    /* Name for PRQ interrupt */
605 	struct completion prq_complete;
606 	struct ioasid_allocator_ops pasid_allocator; /* Custom allocator for PASIDs */
608 	struct iopf_queue *iopf_queue;
609 	unsigned char iopfq_name[16];
610 	struct q_inval  *qi;            /* Queued invalidation info */
611 	u32 *iommu_state; /* Store iommu states between suspend and resume.*/
614 	struct ir_table *ir_table;	/* Interrupt remapping info */
615 	struct irq_domain *ir_domain;
616 	struct irq_domain *ir_msi_domain;
618 	struct iommu_device iommu;  /* IOMMU core code handle */
619 	int		node;
620 	u32		flags;      /* Software defined flags */
622 	struct dmar_drhd_unit *drhd;
623 	void *perf_statistic;