Lines Matching full:a0
35 * a0..a7 is used as register names in the descriptions below, on arm32
85 * a0: INTEL_SIP_SMC_FPGA_CONFIG_START.
91 * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR.
105 * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE.
111 * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or
132 * a0: INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE.
136 * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_BUSY or
156 * a0: INTEL_SIP_SMC_FPGA_CONFIG_ISDONE.
160 * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or
175 * a0:INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM.
179 * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR.
195 * a0: INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK.
199 * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR.
212 * a0: INTEL_SIP_SMC_REG_READ.
217 * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
231 * a0: INTEL_SIP_SMC_REG_WRITE.
237 * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
251 * a0: INTEL_SIP_SMC_REG_UPDATE.
258 * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
271 * a0 INTEL_SIP_SMC_RSU_STATUS
275 * a0: Current Image
282 * a0: INTEL_SIP_SMC_RSU_ERROR
295 * a0 INTEL_SIP_SMC_RSU_UPDATE
300 * a0 INTEL_SIP_SMC_STATUS_OK
313 * a0 INTEL_SIP_SMC_ECC_DBE
318 * a0 INTEL_SIP_SMC_STATUS_OK
333 * a0 INTEL_SIP_SMC_RSU_NOTIFY
338 * a0 INTEL_SIP_SMC_STATUS_OK
350 * a0 INTEL_SIP_SMC_RSU_RETRY_COUNTER
354 * a0 INTEL_SIP_SMC_STATUS_OK
359 * a0 INTEL_SIP_SMC_RSU_ERROR
372 * a0 INTEL_SIP_SMC_RSU_DCMF_VERSION
376 * a0 INTEL_SIP_SMC_STATUS_OK
382 * a0 INTEL_SIP_SMC_RSU_ERROR
394 * a0 INTEL_SIP_SMC_RSU_MAX_RETRY
398 * a0 INTEL_SIP_SMC_STATUS_OK
402 * a0 INTEL_SIP_SMC_RSU_ERROR