Lines Matching +full:itu +full:- +full:r
45 * MST: Multistream Transport - part of DP 1.2a
56 /* bits per component for non-RAW */
186 # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
383 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
438 * VESA DP-to-HDMI PCON Specification adds caps for colorspace
439 * conversion in DFP cap DPCD 83h. Sec6.1 Table-3.
457 /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
458 #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */
463 /* DP-HDMI2.1 PCON DSC Version */
470 /* DP-HDMI2.1 PCON DSC RC Buffer block size */
478 /* DP-HDMI2.1 PCON DSC RC Buffer size */
481 /* DP-HDMI2.1 PCON DSC Slice capabilities-1 */
520 /* DP-HDMI2.1 PCON DSC Slice capabilities-2 */
526 /* DP-HDMI2.1 PCON HDMI TX Encoder Bits/pixel increment */
564 /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
917 /* Source Device-specific */
920 /* Sink Device-specific */
923 /* Branch Device-specific */
937 /* eDP-specific */
1034 /* 0-5 sink count */
1169 /* PCON CONFIGURE-1 FRL FOR HDMI SINK */
1186 /* PCON CONFIGURE-2 FRL FOR HDMI SINK */
1246 * Valid Offsets to be added to Base : 0-127
1251 * Offset-0 8LSBs of the Slice height.
1252 * Offset-1 8MSBs of the Slice height.
1257 * Offset-0 8LSBs of the Slice width.
1258 * Offset-1 8MSBs of the Slice width.
1263 * Offset-0 8LSBs of the bits_per_pixel.
1264 * Offset-1 2MSBs of the bits_per_pixel.
1314 /* LTTPR: Link Training (LT)-tunable PHY Repeaters */
1343 (__DP_LTTPR1_BASE + (__DP_LTTPR2_BASE - __DP_LTTPR1_BASE) * \
1344 ((dp_phy) - DP_PHY_LTTPR1))
1347 (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg))
1385 (__DP_FEC1_BASE + ((__DP_FEC2_BASE - __DP_FEC1_BASE) * \
1386 ((dp_phy) - DP_PHY_LTTPR1)))
1389 (DP_FEC_BASE(dp_phy) - DP_FEC_BASE(DP_PHY_LTTPR1) + fec1_reg)
1430 /* peer device type - DP 1.2a Table 2-92 */
1437 /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
1462 /* DP 1.2 MST sideband nak reasons - table 2.84 */
1479 /* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */
1521 #define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */
1525 /* 0x80+ CEA-861 infoframe types */
1528 * struct dp_sdp_header - DP secondary data packet header
1546 * struct dp_sdp - DP secondary data packet
1551 * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid
1552 * db[2]: CRC value bits 7:0 of the R or Cr component
1553 * db[3]: CRC value bits 15:8 of the R or Cr component
1558 * db[8] - db[31]: Reserved
1560 * db[0] - db[15]: Reserved
1564 * db[19] - db[31]: Reserved
1576 * enum dp_pixelformat - drm DP Pixel encoding formats
1579 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1601 * enum dp_colorimetry - drm DP Colorimetry formats
1604 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1607 * @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or
1608 * ITU-R BT.601 colorimetry format
1610 * @DP_COLORIMETRY_BT709_YCC: ITU-R BT.709 colorimetry format
1612 * (scRGB (IEC 61966-2-2)) colorimetry format
1616 * @DP_COLORIMETRY_DCI_P3_RGB: DCI-P3 (SMPTE RP 431-2) colorimetry format
1620 * @DP_COLORIMETRY_BT2020_RGB: ITU-R BT.2020 R' G' B' colorimetry format
1621 * @DP_COLORIMETRY_BT2020_CYCC: ITU-R BT.2020 Y'c C'bc C'rc colorimetry format
1622 * @DP_COLORIMETRY_BT2020_YCC: ITU-R BT.2020 Y' C'b C'r colorimetry format
1642 * enum dp_dynamic_range - drm DP Dynamic Range
1645 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1657 * enum dp_content_type - drm DP Content Type
1660 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1662 * CTA-861-G defines content types and expected processing by a sink device
1679 * struct drm_dp_vsc_sdp - drm DP VSC SDP
1682 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
1683 * [Table 2-117: VSC SDP Payload for DB16 through DB18]
1685 * @sdp_type: secondary-data packet type
1692 * @content_type: CTA-861-G defines content types and expected processing by a sink device
1773 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & in drm_dp_sink_supports_dsc()
1780 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] | in drm_edp_dsc_sink_output_bpp()
1781 (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & in drm_edp_dsc_sink_output_bpp()
1790 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * in drm_dp_dsc_sink_max_slice_width()
1823 * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support
1845 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
1865 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
1867 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
1879 * struct drm_dp_aux - DisplayPort AUX channel
1893 * @name: user-visible name of this AUX channel and the
1894 * I2C-over-AUX adapter.
1902 * @ddc: I2C adapter that can be used for I2C-over-AUX
1955 * This is a hardware-specific implementation of how
1961 * were transferred, or a negative error-code on failure.
1964 * the %-EBUSY error, which causes a transaction to be retried.
1965 * On a short, helpers will return %-EPROTO to make it simpler
1989 * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
2004 * drm_dp_dpcd_readb() - read a single byte from the DPCD
2019 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
2120 * struct drm_dp_desc - DP branch/sink device descriptor
2133 * enum drm_dp_quirk - Display Port sink/branch device specific quirks
2157 * The device does not set SINK_COUNT to a non-zero value.
2179 * drm_dp_has_quirk() - does the DP device have a specific quirk
2188 return desc->quirks & BIT(quirk); in drm_dp_has_quirk()
2192 * struct drm_edp_backlight_info - Probed eDP backlight info struct
2194 * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any
2270 * struct drm_dp_phy_test_params - DP Phy Compliance parameters